Current-limited latch
View Patent ↗A current-limited latch circuit is used within a nonvolatile memory integrated circuit for decoding, programming, erase, and other operations. In one implementation, there are a number of latches connected together in parallel between two power supply lines. A current mirroring scheme limits current supplied to the latch. This reduces a difference of the two supplies, positive voltage, ground, or negative voltages, during data changes. The circuit provides smaller device sizes and fast speeds when data changes in the latch, while also providing lower power consumption. The technique provides greater benefits as the voltage difference between the two power supplies is greater.
1. An integrated circuit for storage of data comprising:
an array of nonvolatile memory cells;
a plurality of latch circuits coupled to the array of nonvolatile memory cells, the plurality of latch circuits connected in parallel between an upper supply line and a lower supply line, an individual one of the plurality of latch circuits including a pull-up circuit block connected to the upper supply line and a pull-down circuit block connected to the lower supply line;
a first current limiter circuit connected to the upper supply line;
a first current source connected to the first current limiter circuit, the first current limiter circuit interposed between the first current source and the upper supply line to limit a first current from the first current source to the upper supply line;
a second current limiter circuit connected to the lower supply line; and
a second current source connected to the second current limiter circuit, the second current limiter circuit interposed between the second current source and the lower supply line to limit a second current from the second current source to the lower supply line.
2. The integrated circuit of claim 1 wherein the plurality of latch circuits are dedicated to a segment of the memory array.
3. The integrated circuit of claim 2 wherein the segment of the memory array consists of sixty-four rows of memory cells.
4. The integrated circuit of claim 1 wherein the array of nonvolatile memory cells is a NAND array.
5. The integrated circuit of claim 1 wherein the array of nonvolatile memory cells is arranged in rows and columns and individual rows are further divided into a plurality of banks of memory cells.
6. The integrated circuit of claim 5 further comprising a plurality of pass gates, each pass gate corresponding to a bank of memory cells.
7. The integrated circuit of claim 1 wherein individual cells of the nonvolatile memory array contain more than one bit of data.
8. An integrated circuit for storage of data, comprising:
an array of nonvolatile memory cells arranged in rows and columns, a row of cells divided into a plurality of banks of cells, a bank being individually selectable; and
a plurality of latch circuits coupled to the array of nonvolatile memory cells, the plurality of latch circuits connected in parallel between an upper supply line and a lower supply line, an individual latch circuit including a pull-up circuit block connected to the upper supply line and a pull-down circuit block connected to the lower supply line, an individual latch circuit of the plurality of latch circuits being selectably connectable to individual banks of the plurality of banks of cells, the individual latch circuit connected to a first bank at a first time and connected to a second bank at a second time.
9. The integrated circuit of claim 8 further comprising one or more switches interposed between the plurality of latch circuits and the plurality of banks of cells to allow one of the plurality of latch circuits to be connected to a selected individual bank of cells.
10. The integrated circuit of claim 8 further comprising first current source and a first current limiter providing limited current to the upper supply line and a second current source and a second current limiter providing limited current to the lower supply line.
11. A method of accessing data in a nonvolatile memory array, comprising:
providing a first current to an upper supply line through a first current limiter circuit;
providing a second current to a lower supply line through a second current limiter circuit;
providing a plurality of latches between the upper supply line and the lower supply line, an individual one of the plurality of latches including a pull-up circuit block connected to the upper supply line and a pull-down circuit block connected to the lower supply line; and
connecting the plurality of latches to a portion of the nonvolatile memory array.
12. The method of claim 11 wherein the portion of the nonvolatile memory array is a row of the memory array.
13. The method of claim 11 wherein the portion of the nonvolatile memory array is a section of the memory array that consists of multiple rows.
14. The method of claim 11 further comprising, in a first mode, providing the upper supply line with a positive voltage and, in a second mode, providing the upper supply line with a first negative voltage and providing the lower supply line with a second negative voltage that is more negative than the first negative voltage.