Semiconductor device having a retrograde dopant profile in a channel region
View Patent ↗An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.
1. A semiconductor device comprising:
a first transistor element including:
a well structure formed in a substrate;
a diffusion barrier layer formed on said well structure;
a channel layer formed on said diffusion barrier layer;
a gate insulation layer formed on the channel layer;
a gate electrode formed on said gate insulation layer;
a source region and a drain region formed in said well structure and separated by a channel region,
wherein a dopant concentration in the channel region decreases from the gate insulation layer towards the diffusion barrier layer.
2. The semiconductor device of claim 1 , wherein the diffusion barrier layer comprises silicon and germanium.
3. The semiconductor device of claim 2 , wherein approximately 1-30% germanium atoms are provided in the diffusion barrier layer.
4. The semiconductor device of claim 1 , wherein a thickness of the channel layer is in the range of approximately 10-100 nanometers.
5. The semiconductor device of claim 1 , wherein a thickness of the diffusion barrier layer is in the range of approximately 2-20 nanometers.
6. The semiconductor device of claim 1 , wherein the first transistor element is at least one of a P-channel transistor, an N-channel transistor, a high speed short channel transistor and a low leakage transistor.
7. The semiconductor device of claim 1 , further comprising a second transistor element.
8. The semiconductor device of claim 7 , wherein a gate insulation layer of the second transistor element has a thickness that is less than a thickness of the gate insulation layer of the first transistor element.
9. The semiconductor device of claim 7 , wherein the second transistor element is at least one of a P-channel transistor, an N-channel transistor, a high speed short channel transistor and a low leakage transistor.
10. The semiconductor device of claim 7 , further comprising a first die area and a second die area, the first die area containing a plurality of first transistor elements and the second die area containing a plurality of second transistor elements, wherein the second transistor elements each have a thinner gate insulation layer than each of the first transistor elements.
11. The semiconductor device of claim 7 , wherein the first and the second transistor elements form a complementary MOS pair, with the first transistor element being the P-channel transistor.