Organic dielectric electronic interconnect structures and method for making
View Patent ↗A method for making a multi-layer electronic structure. A layer of dielectric material having a top surface and a bottom surface is provided. A layer of electrically conducting material is provided on one of the top surface and the bottom surface of the dielectric layer. At least one passage is formed through the dielectric layer to expose the layer of electrically conducting material. Electrically conducting material is deposited in at least one of the at least one passage through the dielectric layer. Portions of the layer of electrically conducting material are removed to define a pattern of circuitry. A stack is formed of plurality of structures including the layer of dielectric material and layer of electrically conducting material. The plurality of structures are aligned and joined together. Spaces between the structures are filled with electrically insulating material.
1. A parallel joining technology multi-layer electronic structure, comprising:
at least two substructures joined directly together, each substructure comprising a layer of a dielectric material having top and bottom major surfaces, and a pattern of circuitry on at least one of said major surfaces, wherein opposed major surfaces of adjacent substructures define a void therebetween;
at least one passage defined in each said substructure;
a plug of an electrically conductive material in each said passage in electrical contact with said circuitry on said substructure, wherein said plug on a first substructure is in electrical contact with said circuitry on an adjacent substructure; and
a layer of a cured, thermosetting resin filling said void between said adjacent major surfaces.
2. The parallel joining technology multi-layer electronic structure, according to claim 1 , wherein said thermosetting resin includes at least one member selected from the group consisting of epoxy, acrylic, cyanate ester, urethane, polyester, bismaleimide triazine, silicone, and mixtures and copolymers thereof.
3. The parallel joining technology multi-layer electronic structure, according to claim 1 , wherein said dielectric material is selected from the group consisting of free standing organic film, fiber reinforced resin sheet, or particulate filled fluoropolymer sheet, or resin filled expanded fluoropolymer sheet.
4. The parallel joining technology multi-layer electronic structure, according to claim 3 , wherein said free standing organic film is polyimide film.
5. The parallel joining technology multi-layer electronic structure, according to claim 3 , wherein said free standing organic film is a liquid crystal polymer film.
6. The parallel joining technology multi-layer electronic structure, according to claim 3 , wherein said fiber reinforced resin sheet includes at least one of glass aramid, and liquid crystal polymer fibers and the fibers are woven or non-woven.
7. The parallel joining technology multi-layer electronic structure, according to claim 1 , wherein said pattern of circuitry comprises copper.
8. The parallel joining technology multi-layer electronic structure, according to claim 1 , wherein said electrically conducting material comprises a material selected from the group consisting of a plated metal, a plated alloy, a conductive paste having metal particles, at least a portion of which are fusible, present in a volume fraction above a percolation threshold, a conductive paste having fusible metal particles, and a conductive paste having metal particles coated with a fusible metal coating.
9. The parallel joining technology multi-layer electronic structure, according to claim 1 , further comprising a cap on the electrically conducting material in the at least one passage.
10. The parallel joining technology multi-layer electronic structure, according to claim 9 , wherein said cap comprises tin.
11. The parallel joining technology multi-layer electronic structure, according to claim 9 , wherein said cap has a thickness of about 0.0001 inch to about 0.0004 inch.
12. The parallel joining technology multi-layer electronic structure, according to claim 1 , further comprising a layer of tin oxide on the pattern of circuitry.
13. The parallel joining technology multi-layer electronic structure, according to claim 1 , the layer of dielectric material and the pattern of circuitry have been treated in a fluorine-containing plasma prior to stacking and joining the substructures.
14. The parallel joining technology multi-layer electronic structure, according to claim 1 , further comprising an aligning structure for aligning the substructures.
15. The parallel joining technology multi-layer electronic structure, according to claim 1 , further comprising at least one solder joint between adjacent substructures.
16. The parallel joining technology multi-layer electronic structure, according to claim 1 , further comprising at least one semiconductor chip mechanically and electrically joined to said multi-layer electronic structure.
17. The parallel joining technology multi-layer electronic structure, according to claim 1 , wherein said substructures comprise a printed wiring board.
18. The parallel joining technology multi-layer electronic structure, according to claim 17 , further comprising at least one electronic component mechanically and electrically joined to said multi-layer electronic structure.