Semiconductor integrated circuit device having a common DRAM block accessed by a plurality of logic circuits
View Patent ↗A plurality of logic circuits access a DRAM block by way of an access circuit. The operation clock for the DRAM block is set at a higher frequency than the system clock for the logic circuits. Outputs of a first bit width from the logic circuits are subjected to serial/parallel conversion into data of a second bit width and the data is written into the DRAM block.
1. A semiconductor integrated circuit device comprising:
a plurality of logic circuits;
a DRAM block; and
an access circuit for, upon receipt of an instruction from the logic circuits, accessing the DRAM block by performing time division processing,
wherein an operation clock for the DRAM block is set at a higher frequency than an operation clock for the logic circuits.
2. The device of claim 1 , wherein the access circuit includes a serial/parallel conversion circuit, which is provided between the logic circuits and the DRAM block, receives output data from the logic circuits and the DRAM block, converts the number of bits of the received data, and outputs data resulting from the conversion.
3. The device of claim 1 , wherein in writing output data from the logic circuits into the DRAM block, if a destination of the output data is some of entire bits at a write address, the access circuit issues to the DRAM block a write mask command for preventing writing into remaining bit or bits at the write address.
4. A semiconductor integrated circuit device comprising:
first and second logic circuits;
a DRAM block; and
an access circuit for, upon receipt of an instruction from the first and second logic circuits, accessing the DRAM block by performing time division processing,
wherein the access circuit includes:
a first serial/parallel conversion circuit, provided between the first logic circuit and the DRAM block, for receiving output data from the first logic circuit and the DRAM block, converting the number of bits of the received data, and outputting data resulting from the conversion, and
a second serial/parallel conversion circuit, provided between the second logic circuit and the DRAM block, for receiving output data from the second logic circuit and the DRAM block, converting the number of bits of the received data, and outputting data resulting from the conversion; and
the first and second serial/parallel conversion circuits have different conversion rates for converting the number of bits.
5. The device of claim 1 or 4 , wherein the DRAM block includes a plurality of DRAMs.