Extended universal serial bus connectivity
View Patent ↗A system, method and apparatus is provided for extended universal serial bus connectivity. In one embodiment, the invention is an apparatus. The apparatus includes a printed circuit board having a plurality or traces. The plurality of traces includes a first set of traces defining a universal serial bus. The first set of traces is routed between a connector site and an interface circuitry site. The plurality of traces also includes a second set of traces. The second set of traces defines extended signals of the universal serial bus. The second set of traces is routed between the connector site and the interface circuitry site.
1. An apparatus, comprising: a printed circuit board having a plurality of traces, the plurality of traces including a first set of traces including four traces, the first set of traces defining a universal serial bus by defining a power trace, a ground trace, a first data signal and a second data signal, the first set of traces being routed between a first connector site and an interface circuitry site; the first set of traces being also routed between a second connector site and the interface circuitry site, the plurality of traces also including a second set of traces including two traces, the second set of traces defining extended signals of the universal serial bus by including traces for a reset signal and a write protect signal, the second set of traces being routed between the second connector site and the interface circuitry site, wherein the first connector site and the second connector site are spaced apart from one another, further comprising a connector connected to the first connector site, the connector including conductors coupled to the first set of traces.
2. The apparatus of claim 1 , further comprising:
a connector connected to the first connector site, the connector including conductors coupled to the first set of traces.
3. The apparatus of claim 1 , further comprising:
an interface that connects the first connector site to a separate printed circuit board.
4. The apparatus of claim 1 , further comprising:
a FLASH memory chip coupled to the printed circuit board, the memory chip coupled to the interface circuitry site through traces of the printed circuit board.
5. The apparatus of claim 4 , further comprising:
a FLASH memory controller chip coupled to the printed circuit board at the interface circuitry site, the controller chip incorporating interface circuitry.
6. The apparatus of claim 5 , further comprising:
a connector connected to the first connector site, the connector including conductors coupled to the first set of traces.
7. The apparatus of claim 5 , further comprising:
a connector connected to the second connector site, the connector including conductors coupled to the first set of traces and the second set of traces.
8. The apparatus of claim 4 , further comprising:
a FLASH memory controller chip coupled to the printed circuit board electrically between the memory chip and the interface circuitry site.
9. The apparatus of claim 6 , further comprising:
interface circuitry coupled to the printed circuit board at the interface circuitry site, the interface circuitry coupled to the controller chip and to the first connector site and the second connector site.
10. An apparatus, comprising: a printed circuit board having a plurality of traces, the plurality of traces including a first set of traces defining a universal serial bus by defining a power trace, a ground trace, a first data signal and a second data signal, the first set of traces being routed between a connector site and an interface circuitry site, the plurality of traces also including a second set of traces, the second set of traces defining extended signals of the universal serial bus by including traces for a reset signal and a write protect signal, the second set of traces being routed between the connector site and the interface circuitry site, wherein the first connector site and the second connector site are spaced apart from one another, and wherein the first set of traces and the second set of traces are configured to define sets of signal further comprising a FLASH memory chip coupled to the printed circuit board, the memory chip coupled to the interface circuitry site through traces of the printed circuit board.
11. The apparatus of claim 10 , further comprising:
a FLASH memory controller chip coupled to the printed circuit board at the interface circuitry site, the controller chip incorporating interface circuitry.
12. The apparatus of claim 11 , further comprising:
a connector connected to the connector site, the connector including conductors coupled to the first set of traces and the second set of traces.
13. The apparatus of claim 10 , further comprising:
a plurality of FLASH memory chips coupled to the printed circuit board, the plurality of memory chips coupled to the interface circuitry site through traces of the printed circuit board.
14. The apparatus of claim 10 , further comprising:
a FLASH memory controller chip coupled to the printed circuit board electrically between the connector site and the plurality of FLASH memory chips.