Apparatus for frequency dividing a master clock signal by a non-integer
View Patent ↗A frequency dividing circuit divides a master clock frequency by a non-integer factor to provide an output clock signal whose frequency is equal to the frequency of the master clock signal divided by that non-integer factor. In one embodiment, the circuit is operative to divide the master clock frequency by 2.5.
1. A method to generate a frequency divided output clock signal comprising:
performing sequential counting operations based upon a received master clock signal to produce multiple counted outputs;
introducing respective ones of the multiple counted outputs as inputs to respective bi-stable operations;
clocking each of the respective bi-stable operations using phase shifted versions of the master clock signal; and
combining outputs of the respective bi-stable operations to produce a frequency-divided output clock signal.
2. The method of claim 1 , wherein the frequency divided output clock signal comprises a frequency equal to a frequency of the master clock signal divided by a non-integer value.
3. A method for generating a frequency divided output clock signal, comprising:
clocking a counter having multiple outputs using a master clock signal;
introducing respective outputs of the multiple outputs to respective circuit stages;
shifting a phase of the master clock signal to produce a plurality of phase shifted versions thereof;
clocking each of the respective circuit stages using at least one of the phase shifted versions of the master clock signal; and
combining outputs of the respective circuit stages to produce a frequency-divided output clock signal.