Semiconductor wafer, semiconductor chip and method for manufacturing the same
View Patent ↗In a semiconductor device, in which an insulating layer is disposed on the main face of the silicon substrate, and the insulating layer includes the protruding portion that protrudes from the end face of the silicon substrate, the protruding portion has an interconnect of Cu embedded within the insulating layer.
1. A semiconductor wafer comprising:
a semiconductor substrate; and
an insulating film provided on a main face of said semiconductor substrate,
wherein a plurality of element regions and a dicing region are provided on said main face, said dicing region providing an isolation between said plurality of element regions and comprising an interconnect that connects one element region with other element region, and
wherein said semiconductor substrate is removed on said dicing region and said dicing region comprises at least a portion of said insulating film,
wherein a conductive plug is provided in said insulating film in said dicing region.
2. The semiconductor wafer according to claim 1 , wherein plurality of said conductive plug are provided to form an array along said dicing region.
3. The semiconductor wafer according to claim 1 , wherein a width of said dicing region is equal to or larger than 2 μm.
4. A semiconductor chip, wherein said semiconductor chip is provided by dividing said semiconductor wafer according to claim 1 in said dicing region.
5. A semiconductor chip, comprising:
a semiconductor substrate; and
an insulating film provided on said main face of said semiconductor substrate,
wherein said insulating film includes a protruding portion, which protrudes toward outside beyond a periphery edge of said semiconductor substrate,
wherein an interconnect is included within an interior of said protruding portion,
wherein a conductive plug is provided within an interior of said protruding portion.
6. The semiconductor chip according to claim 5 , wherein said protruding portion protrudes from said periphery edge of said semiconductor substrate by equal to or larger than 1 μm.
7. A method for manufacturing a semiconductor wafer, comprising:
forming an interconnect layer on a main face of a semiconductor substrate, said interconnect layer including an interconnect and an insulating film, and said interconnect being embedded within said insulating film and connecting one element region to another element region;
fixing the side of said main face of said semiconductor substrate onto a support substrate; and
selectively thinning a predetermined region within a region that said interconnect is provided from a side of a back surface of said semiconductor substrate while the side of said main face of said semiconductor substrate is fixed onto the support substrate to form a dicing region, wherein said forming said interconnect layer further includes embedding a conductive plug within said insulating film in said dicing region.
8. A method for manufacturing a semiconductor wafer, comprising:
forming an interconnect layer on a main face of a semiconductor substrate, said interconnect layer including an interconnect and an insulating film, and said interconnect being embedded within said insulating film;
fixing the side of said main face of said semiconductor substrate onto a support substrate; and
selectively thinning a predetermined region within a region that said interconnect is provided from a side of a back surface of said semiconductor substrate while the side of said main face of said semiconductor substrate is fixed onto the support substrate to form a dicing region,
wherein said forming said interconnect layer further includes embedding a conductive plug within said insulating film in said dicing region.
9. The method according to claim 8 , wherein said embedding said conductive plug further includes forming plurality of said conductive plug along said dicing region.
10. A method for manufacturing a semiconductor chip, comprising: providing a semiconductor wafer by:
forming an interconnect layer on a main face of a semiconductor substrate, said interconnect layer including an interconnect and an insulating film, and said interconnect being embedded within said insulating film;
fixing the side of said main face of said semiconductor substrate onto a support substrate; and
selectively thinning a predetermined region within a region that said interconnect is provided from a side of a back surface of said semiconductor substrate while the side of said main face of said semiconductor substrate is fixed onto the support substrate to form a dicing region; and
joining said back surface of said semiconductor substrate to a dicing sheet;
removing said support substrate from said main face of said semiconductor substrate that is joined to said dicing sheet; and
dividing said semiconductor wafer into a plurality of semiconductor chips by exerting stress to said semiconductor wafer to break said semiconductor wafer in said dicing region.
11. The method according to claim 7 , wherein said embedding said conductive plug further includes forming a plurality of said conductive plug along said dicing region.
12. A method for manufacturing a semiconductor chip, comprising:
providing a semiconductor wafer by the method for manufacturing the semiconductor wafer according to claim 7 ;
joining said back surface of said semiconductor substrate to a dicing sheet;
removing said support substrate from said main face of said semiconductor substrate that is joined to said dicing sheet; and
dividing said semiconductor wafer into a plurality of semiconductor chips by exerting stress to said semiconductor wafer to break said semiconductor wafer in said dicing region.