This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.
1. A method of reading a magnetic memory, comprising:
selecting a common line associated with a respective magnetic bit of a plurality of magnetic bits, wherein each one of said plurality of magnetic bits is in a respective plane of magnetic bits and is associated with a respective sense line;
selecting a wordline of an access transistor, said access transistor being electrically coupled to each said respective sense line; and
sensing a resistance state of said respective magnetic bit associated with said common line at a bit line coupled to said access transistor,
wherein said respective magnetic bit of said plurality of magnetic bits has a read address consisting of an X, Y, and Z coordinate, where, X, Y and Z are axes in three dimensions and correspond to directions of the common line, the wordline and the bit line.
2. The method of claim 1 , wherein said access transistor is electrically coupled to each said respective sense line by a sense line interconnect.
3. The method of claim 2 , wherein said sense line interconnect connects a stack of the plurality of magnetic bits over a substrate.
4. The method of claim 3 , wherein said common line connects multiple magnetic bits in the Y dimension and said sense line interconnect connects magnetic bits of said plurality of magnetic bits in the Z dimension.
5. A method of reading a memory cell, comprising selecting a first memory cell from a three dimensional memory array having a plurality of memory planes, wherein said first memory cell of a first memory plane is in electrical communication with a read-dedicated sense line interconnect, which electrically connects said first memory cell with at least one second memory cell of a second memory plane, and connecting said sense line interconnect and said first and second memory cells with a read circuit.
6. The method of claim 5 , wherein said three dimensional memory array comprises a plurality of stacked planes of memory cells.
7. The method of claim 6 , wherein said first memory cell and each of said second memory cells are in different planes of said array.
8. The method of claim 5 , wherein said first memory cell is addressed for reading by turning on a wordline and a common line.
9. The method of claim 5 , wherein said first memory cell is an MRAM cell.
10. A method of reading memory stored in a resistive memory cell, comprising:
selecting a common line associated with a respective resistive memory cell, wherein the resistive memory cell is associated with a respective sense line;
selecting a wordline of an access transistor, said access transistor being electrically coupled to the sense line; and
sensing a resistance state of the resistive memory cell associated with the common line at a bit line coupled to the access transistor,
wherein the resistive memory cell has a read address consisting of an X, Y, and Z coordinate, where X, Y and Z are axes in three dimensions and correspond to directions of the common line, the wordline and the bit line.
11. The method of claim 10 , wherein said selecting a bit line designates one of said X, Y, and Z coordinates of said address of the resistive memory cell.
12. The method of claim 11 , wherein said selecting a wordline designates another of the X, Y, and Z coordinates.
13. The method of claim 12 , wherein said selecting a common line designates a third one of the X, Y, and Z coordinates.
14. The method of claim 10 , wherein the resistive memory cell is arranged in a planar array of resistive memory cells.
15. The method of claim 14 , wherein the planar array of resistive memory cells is arranged in a stack of a plurality of planar arrays of resistive memory cells.