Resistor ladder interpolation for subranging ADC
View Patent ↗An analog to digital converter includes a resistive ladder outputting a plurality of reference voltages and a coarse ADC receiving the reference voltages and a voltage input. A plurality of coarse comparators receive an output of the coarse ADC. A switch matrix receives an output of the coarse ADC and the reference voltages. The switch matrix inputs a plurality of control signals for selecting at least two voltage subranges. A fine ADC receives the two voltage subranges and the voltage input. A plurality of fine comparators receive an output of the fine ADC. An encoder converts outputs of the coarse and fine comparators to a digital representation of the voltage input. The voltage subranges are adjacent. Each control signal includes a plurality of control lines for controlling corresponding switches. The switches are field effect transistors.
1. An analog to digital converter (ADC) comprising:
a resistive ladder outputting a plurality of reference voltages by means of m number of taps
wherein m is determined by m=2 N−1 for an N-bit ADC;
a first ADC receiving the plurality of reference voltages and a voltage input;
a first plurality of comparators receiving an output of the first ADC;
a switch matrix receiving an output of the first ADC and the reference voltages,
a second ADC receiving the at least two reference voltages and the voltage input;
a second plurality of comparators receiving an output of the second ADC; and
an encoder converting outputs of the first and second comparators to a digital representation of the voltage input.
2. The analog to digital converter of claim 1 , wherein the the reference voltages from the resistive ladder are not necessarily from adjacent taps.
3. The analog to digital converter of claim 1 , wherein said switch matrix can select at least two reference voltages at the same time.
4. The analog to digital converter of claim 1 , wherein all switches in said switch matrix are used twice to reduce the area used on chip.
5. A method for interpolation of reference ladder voltages for use in analog to digital converters (ADCs) comprising:
outputting a range of reference voltages by means of m number of taps from a resistor ladder wherein m is determined by m=2 N−1 for an N-bit ADC
receiving the reference voltages and a voltage input to a first ADC;
connecting at least two of said m number of taps to a plurality of capacitors
wherein at least two capacitors are of unequal values,
and
at least two of said m number of taps are not adjacent to each other;
outputting the capacitor voltages to at least two coarse comparators;
receiving an output of the first ADC and the reference voltages as an input to a switch matrix;
receiving at least two reference voltages and a voltage input into a second ADC;
inputting the output of the second ADC to a plurality of fine comparators; and
encoding the outputs of the fine and coarse comparators.
6. The method of claim 5 , wherein said first ADC is a coarse ADC.
7. The method of claim 5 , wherein said second ADC is a fine ADC.
8. The method of claim 5 , wherein said switch matrix can select at least two reference voltages at the same time.