Method and apparatus for reliable pulse event detection
View Patent ↗A circuit for detecting asynchronous events includes a first event detection latch; and a second event detection latch coupled to the first event detection latch, wherein the first event detection latch is ready to detect an event when the second event detection latch is being reset and wherein the second event detection latch is ready to detect a next event when the first event detection latch is being reset.
1. A circuit for detecting asynchronous events comprising:
a first event detection latch; and
a second event detection latch coupled to the first event detection latch, wherein the first event detection latch is ready to detect an event when the second event detection latch is being reset and wherein the second event detection latch is ready to detect a next event when the first event detection latch is being reset.
2. The circuit of claim 1 , wherein the first event detection latch is an edge detection latch.
3. The circuit of claim 2 , wherein the first event detection latch detects a rising edge event.
4. The circuit of claim 2 , wherein the first event detection latch detects a falling edge event.
5. The circuit of claim 1 , wherein the second event detection latch is an edge detection latch.
6. The circuit of claim 5 , wherein the second event detection latch detects a rising edge event.
7. The circuit of claim 5 , wherein the second event detection latch detects a falling edge event.
8. The circuit of claim 1 , wherein the first event detection latch is a high level event detection latch.
9. The circuit of claim 2 , wherein the first event detection latch is a low level event detection latch.
10. The circuit of claim 1 , further comprising a third and fourth event detection latches and a programming signal for programming each of the first, second, third, and fourth event detection latches to detect one of the group consisting a rising edge event, a falling edge event, a high level event, and a low level event.
11. The circuit of claim 1 , further comprising a multiplexor coupled to the first and second event detection latches for selecting one of the outputs of the first or second event detection latches.
12. The circuit of claim 1 , further comprising a synchronizer circuit for synchronizing the output of the multiplexor and inputting the synchronized signal to a processor as an interrupt signal.
13. A method for detecting asynchronous events, the method comprising:
detecting a first event by a first event detection circuit;
resetting the first event detection circuit after the first event is detected;
detecting a second event by a second event detection circuit; and
resetting the second event detection circuit after the second event is detected, wherein the first event detection circuit is ready to detect an event when the second event detection circuit is being reset and wherein the second event detection circuit is ready to detect a next event when the first event detection circuit is being reset.
14. The method of claim 13 , further comprising programming the first and second event detection circuits for detecting one of the group consisting a rising edge event, a falling edge event, a high level event, and a low level event.
15. The method of claim 13 , further comprising selecting one of the outputs of the first or second event detection latches.
16. The method of claim 15 , further comprising synchronizing the selected signal and inputting the synchronized signal to a processor as an interrupt signal.
17. A programmable circuit for detecting event signals comprising:
a first programmable event detection circuit for detecting one of the group consisting a rising edge event, a falling edge event, a high level event, and a low level event; and
a second programmable event detection circuit coupled to the first programmable event detection circuit for detecting one of the group consisting a rising edge event, a falling edge event, a high level event, and a low level event, wherein the first and second programmable event detection circuits operate in a ping-pong manner for detecting events.
18. The circuit of claim 17 , further comprising a multiplexor coupled to the first and second event detection circuits for selecting one of the outputs of the first or second event detection circuits.
19. The circuit of claim 17 , further comprising a synchronizer circuit for synchronizing the output of the multiplexor and inputting the synchronized signal to a processor as an interrupt signal.
20. The circuit of claim 19 , wherein the output of the multiplexor is selected by the processor.