Level-conversion circuit
View Patent ↗An independent control signal is transmitted to each of a driver control unit and an output transistor, so as to prevent the driver control unit and the output transistor from being made to operate at the same time and reduce through-current flows. Since the transistor ratio can be selected easily, the degree of designing flexibility increases and the speed enhancement is achieved.
1. A level-conversion circuit, comprising:
an input-timing control unit;
a PMOS-driver control unit;
an NMOS-driver control unit; and
an output unit,
wherein the input-timing control unit receives a small-amplitude signal, as an input signal, and transmits an inverted-input signal generated by inverting the input signal,
wherein the output unit transmits a large-amplitude output signal according to at least two control signals transmitted from the PMOS-driver control unit and the NMOS-driver control unit to which the input signal and the inverted-and-input signal are transmitted, and
wherein:
the output unit further includes a data-holding unit,
each of the control signals transmitted from the PMOS-driver control unit and the NMOS-driver control unit is a one-shot-pulse control signal,
the output unit transmits the large-amplitude output signal due to the one-shot-pulse signal, and
the data-holding unit holds the large-amplitude output signal.
2. The level-conversion circuit according to claim 1 , wherein:
the output unit includes first and second transistors,
when the first transistor is turned on and transmits a
first large-amplitude level signal, the second transistor is turned off, and
when the second transistor is turned on and transmits a second large-amplitude level signal, the first transistor is turned off.
3. The level-conversion circuit according to claim 1 , wherein:
a pulse width of the one-shot-pulse signal corresponds to delay time for generating the inverted-and-input signal.
4. A semiconductor circuit comprising the level-conversion circuit according to claim 1 .
5. A level-conversion circuit, comprising:
an input-timing control unit for receiving third and
fourth power-source-level small-amplitude input signals;
a PMOS-driver control unit;
an NMOS-driver control unit; and
an output unit for transmitting first and second power-source-level large-amplitude output signals, the output unit including a first transistor for transmitting the first power-source-level large-amplitude output signal and a second transistor for transmitting the second power-source-level large-amplitude output signal,
wherein;
when the first transistor is turned on, the second transistor is turned off, and
when the second transistor is turned on, the first transistor is turned off, wherein:
when the small-amplitude input signal is caused to transition from the fourth power-source level to the third power-source level, an output signal transmitted from the PMOS-driver control unit is caused to transition from the first power-source level to the fourth power-source level and caused to transition to the first power-source level after a predetermined time period, and
when the small-amplitude input signal is caused to transition from the third power-source level to the fourth power-source level, an output signal transmitted from the NMOS-driver control unit is caused to transition from the second power-source level to the third power-source level and caused to transition to the second power-source level after another predetermined time period.
6. A level-conversion circuit, comprising:
an input-timing control unit for receiving third and
fourth power-source-level small-amplitude input signals;
a PMOS-driver control unit;
an NMOS-driver control unit; and
an output unit for transmitting first and second power-source-level
large-amplitude output signals, the output unit including a first transistor for transmitting the first power-source-level large-amplitude output signal and a second transistor for transmitting the second power-source-level large-amplitude output signal,
wherein;
when the first transistor is turned on, the second transistor is turned off, and
when the second transistor is turned on, the first transistor is turned off, wherein:
the PMOS-driver control unit comprises:
a third transistor for transmitting the fourth power
source-level output signal to the output unit; and
a fifth transistor,
wherein the fifth transistor stops power transmitted from a first power source for a predetermined time period at the instant when the third transistor is turned on and receives the power transmitted from the first power source over a period of time during the third transistor is turned off,
wherein the NMOS-driver control unit comprises:
a fourth transistor for transmitting the third power-source-level
output signal to the output unit; and
a sixth transistor, and
wherein the sixth transistor stops power transmitted from a second power source for a predetermined time period at the instant when the fourth transistor is turned on and receives the power transmitted from the second power source over a period of time during the fourth transistor is turned off.
7. A level-conversion circuit, comprising:
an input-timing control unit ( 102 ) with an input from an input terminal ( 1 );
a PMOS-driver control unit ( 103 ) connected to the input terminal presenting a small-amplitude input signal, and to an output (N 1 ) of the input-timing control unit presenting the input signal inverted;
an NMOS-driver control unit ( 104 ) connected to the input terminal ( 2 ) presenting the input signal, and to the output (N 1 ) of the input-timing control unit presenting the input signal inverted;
another output (N 2 ) of the input-timing control unit being connected to each of the PMOS-driver control unit and the NMOS-driver control unit, the another output presenting the input signal delayed; and
an output unit ( 105 ) connected to an output (N 3 ) of the PMOS-driver control unit and an output (N 4 ) the NMOS-driver control unit to receive two output control signals,
wherein, the output unit transmits a large-amplitude output signal according to the received two output control signals from the PMOS- and NMOS-driver control units.
8. A level-conversion circuit according to claim 7 , wherein,
the output unit comprises
i) a first output-transistor unit (MP 5 ) connected to the output (N 3 ) of the PMOS-driver control unit,
ii) a second output-transistor (MN 5 ) connected to the output (N 4 ) the NMOS-driver control unit, and
iii) a data-holding unit ( 105 ) connected to outputs of the first and second output-transistor units, and to an output terminal ( 2 ).
9. A level-conversion circuit according to claim 8 , wherein,
the input-timing control unit comprises a first-stage inverter having a PMOS transistor and an NMOS transistor connected to output to a second-stage inverter having another PMOS transistor and another NMOS transistor.
10. A level-conversion circuit according to claim 9 , wherein,
the PMOS-driver control unit ( 103 ) is connected to a power voltage (VDD),
the NMOS-driver control unit ( 104 ) is connected to a ground voltage (VSS), and
the first-stage inverter and the second-stage inverter are each connected to a first voltage lower than the power voltage and a second voltage higher than the ground voltage.
11. A level-conversion circuit according to claim 8 , wherein,
each of the control signals transmitted from the PMOS-driver control unit and the NMOS-driver control unit is a one-shot-pulse control signal,
the output unit transmits the large-amplitude output signal due to the one-shot-pulse signal, and
the data-holding unit holds the large-amplitude output signal.
12. A level-conversion circuit according to claim 7 , wherein,
the output unit comprises a data-holding unit,
each of the control signals transmitted from the PMOS-driver control unit and the NMOS-driver control unit is a one-shot-pulse control signal,
the output unit transmits the large-amplitude output signal due to the one-shot-pulse signal, and
the data-holding unit holds the large-amplitude output signal.