Switch control apparatus, semiconductor device test apparatus and sequence pattern generating program

1. A switch control apparatus for controlling a switch, comprising:

a sequence memory for recording a sequence pattern comprising open/close instruction data which instruct said switch thereon to open/close;

an address control module for sequentially retrieving each of the open/close instruction data of the sequence pattern from said sequence memory; and

an open/close state storage module for storing an open/close state instructed by changed open/close instruction data, when the open/close instruction data retrieved by said address control module is changed,

wherein the open/close state stored by said open/close state storage module is provided to the switch such that the switch opens or closes in response to the open/close state.

2. A switch control apparatus as claimed in claim 1 , wherein said open/close state storage module holds the open/close state stored before a first open/close instruction data is retrieved, while the same data as the first open/close instruction data is consecutively retrieved from the time when the first open/close instruction data of the sequence pattern is retrieved.

3. A switch control apparatus as claimed in claim 2 , wherein said sequence memory stores a plurality of sequence patterns, said address control module retrieves each of the open/close instruction data of the plurality of sequence patterns, and said open/close state storage module holds the open/close state instructed by the last open/close instruction data of another one of the sequence patterns retrieved before one of the sequence patterns is retrieved, while the same data as the first open/close instruction data is consecutively retrieved from the time when the first open/close instruction data of the one of the sequence patterns is retrieved.

4. A switch control apparatus as claimed in claim 1 , wherein said open/close state storage module comprises: a first flip-flop for storing the open/close instruction data retrieved by the address control module; a second flip-flop for storing the open/close instruction data retrieved by said address control module before the open/close instruction data stored by said first flip-flop; and a third flip-flop for storing the open/close state instructed by the open/close instruction data retrieved by said address control module in case the open/close instruction data stored by said first and second flip-flops are different, and said switch opens or closes in response to the open/close state stored by said third flip-flop.

5. A switch control apparatus as claimed in claim 4 , wherein said address control module stores the first open/close instruction data of the sequence pattern in both of said first and second flip-flops.

6. A switch control apparatus as claimed in claim 5 , wherein said address control module retrieves the first open/close instruction data of the sequence pattern within a shorter time than that for the second or later open/close instruction data and stores them in both of said first and second flip-flops.

7. A semiconductor test apparatus for testing a device under test by providing electric power to each part of said device under test, comprising:

a plurality of switches for controlling an electric power input to or output from said device under test;

a first sequence memory for storing a sequence pattern comprising open/close instruction data which instructs said switch to open/close;

a first address control module for sequentially retrieving each of the open/close instruction data of each of the plurality of sequence patterns from said first sequence memory; and

a first open/close state storage module, provided for each of the plurality of switches, for storing an open/close state instructed by changed open/close instruction data, when the open/close instruction data, which instructs said switch to open/close, retrieved by said first address control module is changed,

wherein the open/close state stored by said first open/close state storage module is provided to each of the plurality of switches such that each of the plurality of switches opens or closes in response to the open/close state.

8. A semiconductor test apparatus as claimed in claim 7 , wherein said first sequence memory stores the sequence pattern for each test mode for testing the device under test, and in case the test mode is changed, said first open/close state storage module holds the open/close instruction instructed by a last open/close instruction data of the sequence pattern before the test mode is changed, while the same data as the first open/close instruction data is consecutively retrieved from the time when the first open/close instruction data of the sequence pattern is retrieved after the test mode is changed.

9. A semiconductor test apparatus as claimed in claim 7 , further comprising: a second sequence memory for storing a sequence pattern comprising open/close instruction data, which instructs to open/close other switch than said plurality of switches; a second address control module for sequentially retrieving each of the open/close instruction data of the sequence pattern from said second sequence memory in case an open/close state stored on said first open/close state storage module is changed; and a second open/close state storage module for storing an open/close state instructed by changed open/close instruction data in case the open/close instruction data, which instructs to open/close said other switch, retrieved by said second address control module is changed, wherein said other switch opens or closes in response to the open/close state stored by said second open/close state storage module provided for each of the other switch.

10. A machine readable medium storing thereon a program, which is executable by a processor, including instructions for generating a sequence pattern comprising open/close instruction data, which instructs to open/close a switch, output from a switch control apparatus to said switch, wherein said switch control apparatus comprises:

a sequence memory for recording a sequence pattern comprising open/close instruction data which instructs said switch thereon to open/close;

an address control module for sequentially retrieving each of the open/close instruction data of the sequence pattern from said sequence memory; and

an open/close state storage module for storing an open/close state instructed by changed open/close instruction data, when the open/close instruction data retrieved by said address control module is changed, and

wherein said computer program causes a computer to generate a sequence pattern comprising an open/close instruction data, which is different from an open/close instruction data output when said open/close state storage module starts opening or closing said switch, as an open/close instruction data output until said open/close state storage module starts opening or closing said switch from the time when said address control module starts retrieving the open/close instruction data of the sequence data.