Method and system for in-situ parametric SRAM diagnosis

1. A system for diagnosing a plurality of memory cells in a memory module, the system comprising:

a first multiplexer module for selectively connecting a diagnosis signal in response to at least one multiplexer control signal to a data line associated with a predetermined memory cell; and

a second multiplexer module for connecting the data line to the predetermined memory cell via a bit line in response to one or more bit selection signals for analyzing the same.

2. The system of claim 1 further comprising a complement diagnosis signal connecting to a complement data line via the first multiplexer module.

3. The system of claim 2 further comprising one or more access pads for passing the diagnosis signal and the complement diagnosis signal to or from the first multiplexer module.

4. The system of claim 2 wherein the diagnosis signal and the complement diagnosis signal are controlled and analyzed to obtain a noise margin of the predetermined memory cell.

5. The system of claim 4 further comprising a noise margin map reflecting relations between the noise margin and each corresponding memory cell for the memory module.

6. The system of claim 2 wherein the diagnosis signal and the complement diagnosis signal are controlled and analyzed to obtain a transition voltage associated with the predetermined memory cell.

7. The system of claim 2 wherein the diagnosis signal and the complement diagnosis signal are controlled and analyzed to obtain a bit line split rate associated with the predetermined memory cell.

8. The system of claim 1 wherein the first multiplexer module and the second multiplexer module each further includes one or more bidirectional select gates.

9. The system of claim 1 further comprising at least one test control logic module for generating the multiplexer control signal.

10. The system of claim 1 further comprising an I/O pin associated with the predetermined memory cell for generating the multiplexer control signal.

11. The system of claim 10 wherein the I/O pin and the memory cells are selected by using a joint test action group (JTAG) standard for analyzing the predetermined memory cell.

12. A method for testing a memory module by using a memory testing system, the memory testing system comprising a first multiplexer module for selectively connecting a diagnosis signal to a data line associated with a predetermined memory cell, and a second multiplexer module for connecting the data line to the predetermined memory cell via a bit line, the method comprising:

selecting the predetermined memory cell for testing;

inputting the diagnosis signal to the predetermined memory cell via the first multiplexer module, the second multiplexer module, the data line and the bit line;

reading a complement diagnosis signal resulted from the predetermined memory cell via a complement bit line and a complement data line; and

obtaining at least one characteristic information of the predetermined memory cell based on the complement diagnosis signal and the diagnosis signal.

13. The method of claim 12 wherein the obtaining comprises graphically presenting a relationship between the diagnosis signal and the complement diagnosis signal to obtain a butterfly curve.

14. The method of claim 13 wherein the obtaining comprises deriving a noise margin of the predetermined memory cell based on the butterfly curve.

15. The method of claim 14 further comprising building a map reflecting relations between the noise margin and each corresponding memory cell for the memory module.

16. A method for testing a memory module by using a memory testing system, the memory testing system comprising at least one multiplexer module for selectively creating an access between an access pad and a predetermined memory cell via a bit line associated therewith, the method comprising:

selecting a predetermined memory cell for testing;

writing a high voltage signal representing a value of logic “1” to the predetermined memory cell;

forcing a voltage level on the bit line to decrease;

monitoring a current flow on bit line from the access pad; and

obtaining a transition voltage of the predetermined memory cell when a substantially sharp current transition indicates that the value of the predetermined memory cell has flipped from “1” to “0.”

17. The method of claim 16 further comprising obtaining a device strength of the predetermined memory cell base on a relationship between the current and the voltage level on the bit line.

18. A method for testing a memory module by using a memory testing system, the memory testing system comprising at least one multiplexer module for selectively creating an access between an access pad and a predetermined memory cell via a bit line associated therewith, the method comprising:

selecting a predetermined memory cell for testing;

writing a low voltage signal representing a value of logic “0” to the predetermined memory cell;

forcing a complement voltage level on a complement bit line to decrease;

monitoring a complement current flow on complement bit line from the access pad; and

obtaining a transition voltage of the predetermined memory cell when a substantially sharp current transition indicates that the value of the predetermined memory cell has flipped from “0” to “1.”

19. The method of claim 18 further comprising obtaining a device strength of the predetermined memory cell base on a relationship between the complement current and the complement voltage level on the complement bit line.