IP Library Granted Patent US 7,338,838
Granted Patent B2
US 7,338,838 · App. 11/090,011 · Granted Mar 4, 2008

Resin-encapsulation semiconductor device and method for fabricating the same

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Quick Facts
Patent No.
US 7,338,838
App. No.
11/090,011
Granted
Mar 4, 2008
Kind
B2
Abstract

A resin-encapsulation semiconductor device of this invention includes a die pad for mounting a semiconductor element; a plurality of supporting leads; a semiconductor element; a plurality of leads disposed to have tips thereof opposing the die pad; metal wires; and an encapsulation resin for encapsulating the die pad excluding a bottom thereof, the leads excluding bottoms and outside edges thereof, connecting regions with the metal wires, the supporting leads and the semiconductor element. The outside edges of the leads are disposed on substantially the same plane as the side face of the encapsulation resin, and the tip of each lead has a thin portion where the thickness is reduced in an upper face thereof.

Claims (18)

1. A method for fabricating a resin-encapsulation semiconductor device comprising the steps of:

preparing a lead frame including a die pad provided inside an outer frame made from a plate material for mounting a semiconductor element, supporting leads supporting the die pad at tips thereof and connected to the outer frame at bases thereof, and a plurality of leads arranged to have tips thereof opposing the die pad, connected to the outer frame at bases thereof and having, at the tips thereof, thin portions having a reduced thickness in upper faces thereof;

mounting, on the die pad of the prepared lead frame, a semiconductor element having a principal plane where electrodes are disposed, with the principal plane thereof facing upward;

connecting, through metal wires, the electrodes of the semiconductor element mounted on the die pad to upper faces of the leads of the lead frame in positions other than upper faces of the thin portions; and

resin encapsulating an upper face of the lead frame with an encapsulation resin for encapsulating the die pad excluding a bottom thereof, the leads excluding bottoms thereof, connecting regions with the metal wires, the supporting leads and the semiconductor elements,

wherein each of the tips of the leads opposing the die pad has a thin portion where a thickness is reduced in an upper face thereof, and entire lower faces of the leads are planar.

2. The method for fabricating a resin-encapsulation semiconductor device of claim 1 , further comprising, after the step of resin encapsulating, a step of cutting the bases of the supporting leads and the leads, whereby disposing outside edges of the supporting leads and the leads in substantially the same plane as a side face of the encapsulation resin.

3. The method for fabricating a resin-encapsulation semiconductor device of claim 1 ,

wherein, in the step of mounting a semiconductor element on the die pad, the semiconductor element has such a size as to have a periphery thereof close to the thin portions of the tips of the leads of the lead frame.

4. A method for fabricating a resin-encapsulation semiconductor device comprising the steps of:

preparing a lead frame including a plurality of lead units provided inside an outer frame made from a plate material, each of the lead units including a die pad for mounting a semiconductor element, supporting leads supporting the die pad at tips thereof and connected to the outer frame at bases thereof, and a plurality of leads arranged to have tips thereof opposing the die pad, connected to the outer frame at bases thereof and having, at the tips thereof, thin portions having a reduced thickness in upper faces thereof, and the outer frame having a reduced thickness between the lead units;

mounting, on each die pad of the prepared lead frame, a semiconductor element having a principal plane where electrodes are disposed, with the principal plane thereof facing upward;

connecting, through metal wires, the electrodes of the semiconductor element mounted on the die pad to upper faces of the leads of the lead frame in positions other than upper faces of the thin portions;

resin encapsulating an upper face of the lead frame over the lead unites with an encapsulation resin for encapsulating the die pad excluding a bottom thereof, the leads excluding bottoms thereof, connecting regions with the metal wires, the supporting leads and the semiconductor element; and

cutting the bases of the supporting leads and the leads by cutting the lead frame in portions where the outer frame has the reduced thickness between the lead units, whereby obtaining resin-encapsulation semiconductor devices each of which is in a rectangular parallelepiped shape and has outside edges of the supporting leads and the leads disposed in substantially the same plane as a side face of the encapsulation resin,

wherein each of the tips of the leads opposing the die pad has a thin portion where a thickness is reduced in an upper face thereof, and entire lower faces of the leads are planar.

5. The method for fabricating a resin-encapsulation semiconductor device of claim 4 ,

wherein, in the step of mounting a semiconductor element, the semiconductor element has such a size as to have a periphery thereof close to the thin portions of the tips of the leads of the lead frame.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2016
From: PANNOVA SEMIC, LLC
To: TESSERA ADVANCED TECHNOLOGIES, INC.
Reel/Frame 037581/0466 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2015
From: PANASONIC CORPORATION
To: PANNOVA SEMIC, LLC
Reel/Frame 036065/0273 →
CHANGE OF NAME Recorded Sep 19, 2014
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 033777/0873 →