Efficient decoding
View Patent ↗Embodiments of a method and apparatus for decoding signals are disclosed. The method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of decoding the bits using a first component code, and simultaneously executing the first stage of decoding again using a second component code, and executing a second stage of decoding using the first component code. The first and second stages of decoding are used to generate the bit stream.
1. A method of decoding signals to generate a received bit stream, comprising:
receiving modulated signals;
generating bits representing the signals, and associated reliability of each bit;
operating a first stage of N series-connected decoder stages for decoding the bits, the first stage operating using a first of M component codes; and
operating the N series-connected decoder stages simultaneously, each of the N series-connected decoder stages operating using a different one of M component codes, wherein each of the N series-connected decoder stages use all M component codes for each iteration of decoding, wherein M is at least as great as N, and wherein N is greater than two; and wherein
the plurality of N stages of decoding are used to generate the bit stream.
2. The method of claim 1 , wherein column weights of a parity check matrix of the component codes are non-zero.
3. The method of claim 1 , wherein each component code comprises a regular LDPC, and column weights of a parity matrix of the component codes are pre-selected values.
4. The method of claim 3 , wherein the pre-selected values are all the same.
5. The method of claim 4 , wherein hardware implementing the N series-connected decoder stages includes a repeated structure.
6. The method of claim 5 , wherein a parity check matrix of the component codes has column weights of one.