Test terminal negation circuit for protecting data integrity
View Patent ↗A test terminal negation circuit comprises a switch circuit which receives a test signal from a test terminal and outputs it in an asserted state as it is or in a predetermined negated state to a test object circuit, a test signal control circuit which controls an output signal of the switch circuit to be asserted or negated, a test mode signal generation circuit which generates a test mode signal which asserts the output signal of the switch circuit, and a negating signal generation circuit which can output a negating signal for forcing the output signal of the switch circuit into negated state and comprises an electrically rewritable nonvolatile memory element. When the test signal control circuit receives the negating signal, it does not assert the output signal of the switch circuit even it receives the test mode signal.
1. A test terminal negation circuit comprising:
a switch circuit which receives a test signal from one or more test terminals and outputs it in an asserted state as it is or in a predetermined negated state to a test object circuit;
a test signal control circuit which controls an output signal of the switch circuit to be in the asserted state or in the negated state;
a test mode signal generation circuit which generates a test mode signal which asserts the output signal of the switch circuit and outputs it to the test signal control circuit at the time of a test mode; and
a negating signal generation circuit which can output a negating signal for forcing the output signal of the switch circuit into the negated state to the test signal control circuit and comprises an electrically rewritable nonvolatile memory element, wherein
when the negating signal is outputted from the negating signal generation circuit, the test signal control circuit negates the output signal of the switch circuit even when the test mode signal is outputted from the test mode signal generation circuit.
2. The test terminal negation circuit according to claim 1 , wherein
the negating signal generation circuit comprises a first nonvolatile memory element and a second nonvolatile memory element which have a MOSFET structure, a first inverter circuit and a second inverter circuit,
sources of the first nonvolatile memory element and the second nonvolatile memory element are connected to a ground voltage, gates of the first nonvolatile memory element and the second nonvolatile memory element are connected to a power supply voltage, a drain of the first nonvolatile memory element is connected to an input of the first inverter circuit and an output of the second inverter circuit, and a drain of the second nonvolatile memory element is connected to an output of the first inverter circuit and an input of the second inverter circuit, and
the output of either the first inverter circuit or the second inverter circuit is an output of the negating signal generation circuit.
3. The test terminal negation circuit according to claim 2 , wherein
an output level of the negating signal generation circuit is varied by a threshold voltage difference between the first nonvolatile memory element and the second nonvolatile memory element.
4. A method of negating a test signal comprising:
a step of using the test terminal negation circuit according to claim 1 , and
a step of outputting the negating signal by performing electrical rewriting to the nonvolatile memory element in the negating signal generation circuit after a test is completed.
5. A method of negating a test signal comprising:
a step of using the test terminal negation circuit according to claim 2 ; and
a step of outputting the negating signal by performing electrical rewriting to either the first nonvolatile memory element or the second nonvolatile memory element in the negating signal generation circuit after a test is completed.
6. A nonvolatile semiconductor memory device comprising the test terminal negation circuit according to claim 1 .
7. An IC card comprising the nonvolatile semiconductor memory device according to claim 6 .