Using a bit specific reference level to read a resistive memory
View Patent ↗A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments.
1. A memory comprising:
an array of cells; and
a sense amplifier coupled to said array of cells, to sense a state of a selected cell using two different reference levels after reducing the read current on an addressed line.
2. The memory of claim 1 wherein said memory is a phase change memory.
3. The memory of claim 1 wherein said array of cells includes addressed lines including a reference generator coupled to the addressed line of a cell to be sensed.
4. The memory of claim 3 wherein said reference generator generates a reference voltage for said sense amplifier, said reference generator to change the level of a signal from said addressed line.
5. The memory of claim 4 wherein said reference generator stores a reference level from said addressed line.
6. The memory of claim 5 wherein said reference generator holds and outputs the reference level for comparison after a time delay.
7. The memory of claim 6 , wherein the reference level is stored at a read current that is different from the read current used to generate a comparison voltage.
8. The memory of claim 1 wherein said sense amplifier senses whether the level on a selected addressed line is above or below a reference level.
9. The memory of claim 1 wherein said sense amplifier compares a level on the addressed line at two different times.
10. The memory of claim 1 wherein said memory is a phase change memory and a higher reference voltage is utilized to sense a cell in its higher resistance state and a lower reference voltage is utilized to sense a cell in its lower resistance state.
11. The memory of claim 1 , wherein said memory including the addressed line, a cell to be sensed on the addressed line, wherein said sense amplifier compares a reference voltage generated before a read current to the addressed line of the cell to be sensed is reduced, to a reference voltage generated on the addressed line of the cell to be sensed after the read current is reduced.