IP Library Granted Patent US 7,352,015
Granted Patent B2
US 7,352,015 · App. 11/096,505 · Granted Apr 1, 2008

Gallium nitride materials and methods associated with the same

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Quick Facts
Patent No.
US 7,352,015
App. No.
11/096,505
Granted
Apr 1, 2008
Kind
B2
Abstract

Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.

Claims (59)

1. A semiconductor structure comprising:

a silicon substrate having a top surface;

an amorphous silicon nitride-based material layer formed directly on a majority of the top surface of the substrate;

a nitride-based material overlying layer formed directly on the silicon nitride-based material layer; and

a gallium nitride material region formed over the overlying layer.

2. The structure of claim 1 , wherein the silicon nitride-based material layer is formed directly on the entire top surface of the substrate.

3. The structure of claim 1 , wherein the silicon nitride-based material layer comprises SiN.

4. The structure of claim 1 , wherein the overlying layer is a single crystal.

5. The structure of claim 1 , wherein the overlying layer is formed at temperatures of greater than about 700° C.

6. The structure of claim 1 , wherein the overlying layer comprises an aluminum nitride-based material.

7. The structure of claim 1 , wherein the overlying layer has an epitaxial relationship with the substrate.

8. The structure of claim 1 , wherein the overlying layer comprises a gallium nitride material alloy.

9. The structure of claim 1 , wherein the overlying layer is compositionally-graded.

10. The structure of claim 1 , further comprising a transition layer formed over the overlying layer.

11. The structure of claim 10 , wherein the transition layer is compositionally-graded.

12. The structure of claim 11 , wherein the compositionally-graded transition layer is formed directly on the overlying layer.

13. The structure of claim 11 , wherein the compositionally-graded transition layer comprises Al x Ga (1−x) N and x is decreased from a back surface of the transition layer to a front surface of the transition layer.

14. The structure of claim 1 , wherein the silicon nitride-based material layer has a thickness of less than 100 Angstroms.

15. The structure of claim 1 , wherein the silicon nitride-based material layer has a thickness of greater than 10 Angstroms.

16. The structure of claim 1 , wherein the silicon nitride-based material layer has a thickness between about 10 Angstroms and about 50 Angstroms.

17. The structure of claim 1 , wherein the substrate has a thickness of greater than about 125 micron.

18. The structure of claim 1 , wherein the gallium nitride material region includes a GaN layer.

19. The structure of claim 1 , wherein the overlying layer has a misfit dislocation density of less than about 10 10 defects/cm 2 .

20. The structure of claim 1 , wherein the structure is a FET.

21. The structure of claim 1 , wherein the entire top surface of the silicon nitride-based material layer has a uniform composition.

22. The structure of claim 21 , wherein the entire top surface of the strain-absorbing layer comprises Si x N y .

23. The structure of claim 1 , further comprising a source electrode, a gate electrode and a drain electrode formed on the gallium nitride material region.

24. A semiconductor structure comprising:

a silicon substrate including a top surface;

a silicon nitride-based material layer having a thickness of less than 100 Angstroms and formed directly on a majority of the top surface of the substrate; and

a single crystal aluminum nitride-based material overlying layer formed directly on the silicon nitride-based material layer; and

a gallium nitride material region formed over the overlying layer.

25. The structure of claim 24 , wherein the silicon nitride-based material layer has an amorphous structure.

26. The structure of claim 24 , wherein the silicon nitride-based material layer is formed directly on the entire top surface of the substrate.

27. The structure of claim 24 , further comprising a transition layer formed over the overlying layer.

28. The structure of claim 25 , wherein the transition layer is a compositionally-graded transition layer comprising Al x Ga (1−x) N and x is increased from a back surface of the transition layer to a front surface of the transition layer.

29. The structure of claim 24 , wherein the silicon nitride-based material layer has a thickness of greater than 10 Angstroms.

30. The structure of claim 24 , wherein the substrate has a thickness of greater than about 125 micron.

31. The structure of claim 24 , wherein the gallium nitride material region includes a GaN layer.

32. The structure of claim 24 , wherein the overlying layer has a misfit dislocation density of less than about at 10 10 defects/cm 2 .

33. The structure of claim 24 , wherein the entire top surface of the silicon nitride-based material layer has a uniform composition.

34. The structure of claim 33 , wherein the entire top surface of the strain-absorbing layer comprises Si x N y .

35. The structure of claim 24 , further comprising a source electrode, a gate electrode and a drain electrode formed on the gallium nitride material region.

36. A semiconductor structure comprising:

a silicon substrate including a top surface;

an amorphous silicon nitride-based material layer formed directly on the entire top surface of the silicon substrate and having a thickness of less than 100 Angstroms;

a nitride-based material overlying layer formed on the amorphous silicon nitride-based material layer; and

a gallium nitride material region formed on the overlying layer.

37. The structure of claim 36 , wherein the entire top surface of the silicon nitride-based material layer has a uniform composition.

38. The structure of claim 37 , wherein the entire top surface of the strain-absorbing layer comprises Si x N y .

39. The structure of claim 36 , further comprising a source electrode, a gate electrode and a drain electrode formed on the gallium nitride material region.

40. The structure of claim 36 , wherein the overlying layer is a single crystal.

41. The structure of claim 36 , wherein the overlying layer is formed at temperatures of greater than about 700° C.

42. The structure of claim 36 , wherein the overlying layer comprises an aluminum nitride-based material.

43. The structure of claim 36 , wherein the overlying layer has an epitaxial relationship with the substrate.

44. The structure of claim 36 , wherein the overlying layer comprises a gallium nitride material alloy.

45. The structure of claim 36 , wherein the silicon nitride-based material layer has a thickness of greater than 10 Angstroms.

46. The structure of claim 36 , wherein the silicon nitride-based material layer has a thickness between about 10 Angstroms and about 50 Angstroms.

47. The structure of claim 36 , wherein the gallium nitride material region includes a GaN layer.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2019
From: INFINEON TECHNOLOGIES AMERICAS CORP.
To: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
Reel/Frame 047908/0204 →
CHANGE OF NAME Recorded Jul 23, 2018
From: INTERNATIONAL RECTIFIER CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 046612/0968 →
CONFIDENTIAL EXCLUSIVE LICENSE AND IP PURCHASE AGREEMENTS THAT RESTRICT PATENT ASSIGNMENT BY CURRENT OWNER (ONLY NON-CONFIDENTIAL, PUBLIC MATERIALS SUMMARIZING AGREEMENTS AND LITIGATION DISPUTES RELATING TO THE SAME ATTACHED) Recorded Nov 3, 2017
From: INTERNATIONAL RECTIFIER CORPORATION
To: NITRONEX LLC; MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
Reel/Frame 044532/0627 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2010
From: NITRONEX CORPORATION
To: INTERNATIONAL RECTIFIER CORPORATION
Reel/Frame 024953/0770 →
RELEASE OF SECURITY INTEREST Recorded Aug 5, 2010
From: SILICON VALLEY BANK
To: NITRONEX CORPORATION
Reel/Frame 024794/0055 →
SECURITY AGREEMENT Recorded May 4, 2010
From: NITRONEX CORPORATION
To: SILICON VALLEY BANK
Reel/Frame 024320/0896 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2006
From: PINER, EDWIN L.; ROBERTS, JOHN C.; RAJAGOPAL, PRADEEP
To: NITRONEX CORPORATION
Reel/Frame 017381/0153 →
SECURITY AGREEMENT Recorded Nov 3, 2005
From: NITRONEX CORPORATION
To: SILICON VALLEY BANK
Reel/Frame 016722/0472 →