Anti-eclipse circuitry with tracking of floating diffusion reset level
View Patent ↗An anti-eclipse circuit for an imager is formed from pixel circuitry over the same semiconductor substrate as the imaging pixels. More specifically, two adjacent pixel circuits are modified to form an amplifier. One input of the amplifier is adapted to receive a reset signal from one of the pixel circuits while another input is adapted to be set at a predetermined offset voltage from the output of the amplifier. The amplifier is preferably a unity gain amplifier, so that the output of the amplifier set to a voltage level equal to the predetermined offset from the voltage level of the reset signal. Accordingly, the anti-eclipse circuit outputs a reference voltage at predetermined level from the reset voltage of a pixel and does not need to be calibrated for fabrication related variances in reset voltages.
1. An imager circuit comprising:
an array of pixels including a plurality of imaging pixels for producing respective reset signals and image output signals;
an anti-eclipsing circuit for adjusting the level of said reset signals and utilizing a reference voltage; and
a reference voltage generation circuit for generating said reference voltage in response to signals which are affected by fabrication conditions which affect the reset signal produced by said imaging pixels, the reference voltage generation circuit comprising:
at least one non-imaging pixel for producing a nominal reset signal; and
a voltage circuit for producing said reference voltage as an offset from a voltage level of said nominal reset signal.
2. The imager circuit of claim 1 , wherein said array of pixels, said anti-eclipsing circuit, and said reference voltage generation circuit are located on a same integrated circuit.
3. The imager circuit of claim 1 , wherein said at least one non-imaging pixel further comprises:
a floating diffusion node; and
a transfer transistor, coupled by its source and drain between a light sensitive element and said floating diffusion node, said transfer transistor having a gate coupled to a potential source causing said transfer transistor to remain in a non-conducting state.
4. The imager circuit of claim 1 , said reference voltage generation circuit further comprising a load circuit coupled to said non-imaging pixel for receiving said nominal reset signal, and
wherein said voltage circuit comprises:
a current mirror for producing a mirrored signal identical to said nominal reset signal; and
an offset circuit for producing said reference voltage as an offset from a voltage level of said mirrored signal.
5. The imager circuit of claim 4 , wherein said offset circuit further comprises a transistor, said transistor having a first source/drain coupled to receive said mirrored signal, a second source/drain coupled to said load circuit, and a gate coupled to an offset voltage generator for creating an offset voltage between said first source/drain and said gate.
6. The imager circuit of claim 5 , wherein said offset voltage generator comprises an digital to analog converter, said digital to analog converter having an analog output coupled to said gate of said transistor and a ground power terminal coupled to said first source/drain.
7. The imager circuit of claim 1 , further comprising a sample-and-hold circuit, coupled to said reference voltage generation circuit, said sample-and-hold circuit adapted to sample and hold said reference voltage.
8. An imager comprising:
an array of pixels including a plurality of imaging pixels for producing respective reset signals and image output signals;
a column circuit, coupled to said array of pixels, for selecting a row of pixels from said array for processing;
a plurality of anti-eclipsing circuits for adjusting the level of said reset signals received from the selected row of pixels and utilizing a reference voltage; and
a reference voltage generation circuit for generating said reference voltage in response to signals which are affected by fabrication conditions which affect the reset signal produced by said imaging pixels, the reference voltage generation circuit comprising:
at least one optically black pixel for producing a nominal reset signal; and
a voltage circuit for producing said reference voltage as an offset from a voltage level of said nominal reset signal.
9. The imager of claim 8 , wherein said array of pixels, said anti-eclipsing circuits, and said reference voltage generation circuit are located on a same integrated circuit.
10. The imager of claim 8 , wherein said at least one optically black pixel further comprises:
a floating diffusion node; and
a transfer transistor coupled by its source and drain between a light sensitive element and said floating diffusion node, said transfer transistor having a gate coupled to a potential source causing said transfer transistor to remain in a non-conducting state.
11. The imager of claim 8 , said reference voltage generation circuit further comprising a load circuit coupled to said optically black pixel for receiving said nominal reset signal, and
wherein said voltage circuit comprises:
a current mirror for producing a mirrored signal identical to said nominal reset signal; and
an offset circuit for producing said reference voltage as an offset from a voltage level of said mirrored signal.
12. The imager of claim 11 , wherein said offset circuit further comprises a transistor, said transistor having a first source/drain coupled to receive said mirrored signal, a second source/drain coupled to said load circuit, and a gate coupled to an offset voltage generator for creating an offset voltage between said first source/drain and said gate.
13. The imager of claim 12 , wherein said offset voltage generator comprises a digital to analog converter, said digital to analog converter having an analog output coupled to said gate of said transistor and a negative output terminal coupled to said first source/drain.
14. The imager of claim 8 , further comprising a sample-and-hold circuit, coupled to said reference voltage generation circuit, said sample-and-hold circuit adapted to sample and hold said reference voltage.
15. An imaging system comprising:
a processor; and
an imager, coupled to said processor, said imager comprising:
an array of pixels including a plurality of imaging pixels for producing respective reset signals and image output signals;
a column circuit, coupled to said array of pixels, for selecting a row of pixels from said array for processing;
a plurality of anti-eclipsing circuits for adjusting the level of said reset signals received from the selected row of pixels and utilizing a reference voltage; and
a reference voltage generation circuit for generating said reference voltage in response to signals which are affected by fabrication conditions which affect the reset signal produced by said imaging pixels, the reference voltage generation circuit comprising:
at least one non-imaging pixel for producing a nominal reset signal; and
a voltage circuit for producing said reference voltage as an offset from a voltage level of said nominal reset signal.
16. The imaging system of claim 15 , wherein said array of pixels, said anti-eclipsing circuits, and said reference voltage generation circuit are located on a same integrated circuit.
17. The imaging system of claim 15 , wherein said at least one non-imaging pixel further comprises:
a floating diffusion node; and
a transfer transistor, coupled by its source and drain between a light sensitive element and said floating diffusion node, said transfer transistor having a gate coupled to a potential source causing said transfer transistor to remain in a non-conducting state.
18. The imaging system of claim 15 , further comprising a load circuit, coupled to said non-imaging pixel for receiving said nominal reset signal, and
wherein said voltage circuit comprises:
a current mirror for producing a mirrored signal identical to said nominal reset signal; and
an offset circuit for producing said reference voltage as an offset from a voltage level of said mirrored signal.
19. The imaging system of claim 18 , wherein said offset circuit further comprises a transistor, having a first source/drain coupled to receive said mirrored signal, a second source/drain coupled to said load circuit, and a gate coupled to an offset voltage generator for creating an offset voltage between said first source/drain and said gate.
20. The imaging system of claim 19 , wherein said offset voltage generator comprises a digital to analog converter, said digital to analog converter having an analog output coupled to said gate of said transistor and a ground power terminal coupled to said first source/drain.
21. The imaging system of claim 15 , further comprising a sample-and-hold circuit, coupled to said reference voltage generation circuit, said sample-and-hold circuit adapted to sample and hold said reference voltage.
22. A method for forming an imaging circuit, comprising:
providing a semiconductor substrate;
forming, over said semiconductor substrate, an array of pixels including a plurality of imaging pixels for producing respective reset signals and image output signals, said imaging pixels configured to produce said image output signals according to incident light;
forming, over said semiconductor substrate, an anti-eclipsing circuit for adjusting the level of said reset signals and utilizing a reference voltage;
forming, over said semiconductor substrate, a reference voltage generation circuit for generating said reference voltage in response to signals which are affected by fabrication conditions which affect the reset signal produced by said imaging pixels, the reference voltage generation circuit comprising:
at least one non-imaging pixel for producing a nominal reset signal, said at least one non-imaging pixel configured to not produce an image output signal according to incident light; and
a voltage circuit for producing said reference voltage as an offset from a voltage level of said nominal reset signal; and
forming an integrated circuit using said semiconductor substrate.