Methods and apparatus for providing data transfer control
A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel. Dual transfer execution units within each transfer controller, together with independent transfer counters, are employed to allow decoupling of source and destination address generation and to allow multiple transfer instructions in one transfer execution unit to operate in parallel with a single transfer instruction in the other transfer unit. Improved flow control of data between a source and destination is provided through the use of special semaphore operations, signals and message synchronization which may be invoked explicitly using SIGNAL and WAIT type instructions or implicitly through the use of special “event-action” registers. Transfer controllers are also described which can cooperate to perform “DMA-to-DMA” transfers. Message-level synchronization can be used by transfer controllers to synchronize with each other.
1. A method of transfer control operation comprising the steps of:
detecting a transfer controller reset event;
comparing a transfer program counter value with a wait program counter value;
updating either one of the transfer program counter value or the wait program counter value;
determining that the transfer program counter value and the wait program counter value are not equal; and
placing a transfer controller in a fetch state upon said determination.
2. The method of claim 1 further comprising the steps of fetching and decoding an instruction word.
3. The method of claim 2 wherein if an instruction comprises multiple words, repeating the step of decoding until all the multiple words are decoded.
4. The method of claim 2 further comprising the step of incrementing the transfer counter by one each time a word is fetched.
5. The method of claim 2 further comprising the steps of determining that a fetched instruction is a control type instruction; transitioning to an execute control state; and performing an action specified by the fetched instruction.
6. The method of claim 2 further comprising the steps of executing a wait type instruction and causing a transfer controller to transition to a wait state.