Patent Assignment
Reel/Frame 018184/0423
Assignment of Assignor's Interest
Recorded: 2006-08-29
Pages: 21
Assignor
PTS CORPORATION
Executed: 2006-08-24
Assignee
ALTERA CORPORATION
101 INNOVATION DRIVE, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(96)
Hot Chips & Salsas Inc
Patent:
6,023,753 →
Application:
08/885,310 →
Method and Apparatus for Manifold Array Processing
Patent:
6,167,502 →
Application:
08/949,122 →
Merged Array Controller and Processing Element
Patent:
6,219,776 →
Application:
09/169,072 →
Methods and Apparatus for Dynamic Instruction Controlled Reconfiguration Register File with Extended Precision
Patent:
6,343,356 →
Application:
09/169,255 →
Methods and Apparatus for Manarray Pe-Pe Switch Control
Patent:
6,167,501 →
Application:
09/169,256 →
Methods and Apparatus for Efficient Synchronous Mimd Operations with Ivliw Pe-to-Pe Communication
Patent:
6,151,668 →
Application:
09/187,539 →
Methods and Apparatus for Dynamic Very Long Instruction Word Sub-Instruction Selection for Execution Time Parallelism in an Indirect Very Long Instruction Word Processor
Patent:
6,173,389 →
Application:
09/205,588 →
Methods and Appartus for Scalable Instruction Set Architecture with Dynamic Compact Instructions
Patent:
6,101,592 →
Application:
09/215,081 →
Methods and Apparatus to Dynamically Reconfigure the Instruction Pipeline of an Indirect Very Long Instruction Word Scalable Processor
Patent:
6,216,223 →
Application:
09/228,374 →
Methods and Apparatus to Support Conditional Execution in a Vliw-Based Array Processor with Subword Execution
Patent:
6,366,999 →
Application:
09/238,446 →
Register File Indexing Methods and Apparatus for Providing Indirect Control of Register Addressing in a Vliw Processor
Patent:
6,446,190 →
Application:
09/267,570 →
Manifold Array Processor
Patent:
6,338,129 →
Application:
09/323,609 →
Efficient Complex Multiplication and Fast Fourier Transform (Fft) Implementation on the Manarray Architecture
Methods and Apparatus for Instruction Addressing in Indirect Vliw Processors
Patent:
6,356,994 →
Application:
09/350,191 →
Methods and Apparatus for Abbreviated Instruction Sets Adaptable to Configurable Processor Architectures
Patent:
6,408,382 →
Application:
09/422,015 →
Methods and Apparatus for Improved Motion Estimation for Video Encoding
Patent:
6,697,427 →
Application:
09/432,705 →
Methods and Apparatus for Providing Data Transfer Control
Patent:
6,260,082 →
Application:
09/471,217 →
Methods and Apparatus for Providing Direct Memory Access Control
Patent:
6,256,683 →
Application:
09/472,372 →
Methods and apparatus for scalable instruction set architecture with dynamic compact instructions
Patent:
6,321,322 →
Application:
09/543,473 →
Accessing Tables in Memory Banks Using Load and Store Address Generators Sharing Store Read Port of Compute Register File Separated from Address Register File
Patent:
6,397,324 →
Application:
09/596,103 →
Methods and Apparatus for Establishing Port Priority Functions in a Vliw Processor
Patent:
6,654,870 →
Application:
09/598,084 →
Method and Apparatus for Providing Manifold Array (Manarray) Program Context Switch with Array Reconfigurable Control
Patent:
6,868,490 →
Application:
09/598,558 →
Methods and Apparatus for Initiating and Resysnchronizing Multi-Cycle Simd Instructions
Patent:
6,622,234 →
Application:
09/598,564 →
Specifying Different Type Generalized Event and Action Pair in a Processor
Patent:
6,735,690 →
Application:
09/598,566 →
Methods and Apparatus for Improved Efficiency in Pipeline Simulation and Emulation
Patent:
6,826,522 →
Application:
09/598,567 →
Constructing Database Representing Manifold Array Architecture Instruction Set for Use in Support Tool Code Creation
Patent:
6,748,517 →
Application:
09/599,980 →
Methods and apparatus for manarray PE-PE Switch control
Patent:
6,366,997 →
Application:
09/649,647 →
Methods and Apparatus for Efficient Synchronous Mimd Operations with Ivliw Pe-to-Pe Communication
Patent:
6,446,191 →
Application:
09/677,732 →
Methods and Apparatus for Manifold Array Processing
Patent:
6,470,441 →
Application:
09/707,209 →
Methods and Apparatus for Efficient Cosine Transform Implementations
Patent:
6,754,687 →
Application:
09/711,218 →
Methods and Apparatus for Dynamic Very Long Instruction Word Sub-Instruction Selection for Execution Time Parallelism in an Indirect Very Long Instruction Word Processor
Patent:
6,467,036 →
Application:
09/717,992 →
Methods and Apparatus for Loading a Very Long Instruction Word Memory
Merged Control / Process Element Processor for Executing Vliw Simplex Instructions with Sisd Control / Simd Process Mode Bit
Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response
Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing Dma Controller
Control processor dynamically loading shadow instruction register associated with memory entry of coprocessor in flexible coupling mode
Methods and Apparatus for Dynamic Instruction Controlled Reconfigurable Register File with Extended Precision
Methods and Apparatus to Dynamically Reconfigure the Instruction Pipeline of an Indirect Very Long Instruction Word Scalable Processor
Methods and Apparatus for Power Control in a Scalable Array of Processor Elements
Methods and Apparatus for Providing Direct Memory Access Control
Methods and Apparatus for Indirect Vliw Memory Allocation
Methods and Apparatus for Providing Data Transfer Control
Methods and Apparatus for Scalable Instruction Set Architecture with Dynamic Compact Instructions
Methods and Apparatus for Efficient Complex Long Multiplication and Covariance Matrix Implementation
Methods and Apparatus for Providing Improved Physical Designs and Routing with Reduced Capacitive Power Dissipation
Methods and Apparatus for Efficient Vocoder Implementations
Manifold Array Processor
Methods and Apparatus for Instruction Addressing in Indirect Vliw Processors
Methods and Apparatus for Manarray Pe-Pe Switch Control
Methods and Apparatus to Support Conditional Execution in a Vliw-Based Array Processor with Subword Execution
Methods and Apparatus for Automated Generation of Abbreviated Instruction Set and Configurable Processor Architecture
Methods and Apparatus for Pipelined Bus
Methods and Apparatus for Removing Compression Artifacts in Video Sequences
Methods and Apparatus for Dynamic Very Long Instruction Word Sub-Instruction Selection for Execution Time Parallelism in an Indirect Very Long Instruction Word Processor
Methods and Apparatus for Manifold Array Processing
Methods and Apparatus for Providing Data Transfer Control
Methods and apparatus for a bit rake instruction
Application:
10/282,919 →
Publication:
US 2003/0105945
Methods and Apparatus for Multiple Stage Video Decoding
Processor Efficient Transformation and Lighting Implementation for Three Dimensional Graphics Utilizing Scaled Conversion Instructions
Methods and Apparatus for Scalable Instruction Set Architecture with Dynamic Compact Instructions
Merged Control/Process Element Processor for Executing Vliw Simplex Instructions with Sisd Control/Simd Process Mode Bit
Methods and Apparatus for Initiating and Resynchronizing Multi-Cycle Simd Instructions
Methods and Apparatus to Support Conditional Execution in a Vliw-Based Array Processor with Subword Execution
Methods and Apparatus to Support Conditional Execution in a Vliw-Based Array Processor with Subword Execution
Methods and Apparatus for Establishing Port Priority Functions in a Vliw Processor
Methods and Apparatus to Support Conditional Execution in a Vliw-Based Array Processor with Subword Execution
Methods and Apparatus for Indirect Compound Vliw Execution Using Operand Address Mapping Techniques
Patent:
7,272,700 →
Application:
10/745,267 →
Methods and Apparatus for Loading a Very Long Instruction Word Memory
Patent:
6,883,088 →
Application:
10/758,348 →
Methods and Apparatus for Providing Context Switching Between Software Tasks with Reconfigurable Control
Methods and Apparatus for Storing Expanded Width Instructions in a Vliw Memory for Deferred Execution
Manifold Array Processor
Methods and Apparatus for Providing Data Transfer Control
Cascaded Event Detection Modules for Generating Combined Events Interrupt for Processor Action
System Core for Transferring Data Between an External Device and Memory
Patent:
7,266,620 →
Application:
10/797,726 →
Methods and Apparatus for Single Stage Galois Field Operations
Patent:
7,464,128 →
Application:
10/799,316 →
Methods and Apparatus for Adapting Pipeline Stage Latency Based on Instruction Type
Patent:
7,809,932 →
Application:
10/805,803 →
Methods and Apparatus for Address Translation Functions
Patent:
7,945,760 →
Application:
10/815,294 →
Methods and Apparatus for Providing Direct Memory Access Control
Patent:
40,213 →
Application:
10/819,885 →
Methods and Apparatus for Dynamic Instruction Controlled Reconfigurable Register File with Extended Precision
Patent:
40,883 →
Application:
10/827,697 →
Methods and Apparatus for Abreviated Instruction Sets Adaptable to Configurable Processor Architecture
Patent:
40,509 →
Application:
10/848,615 →
Efficient Complex Multiplication and Fast Fourier Transform (Fft) Implementation on the Manarray Architecture
Register File Indexing Methods and Apparatus for Providing Indirect Control of Register Addressing in a Vliw Processor
Patent:
41,012 →
Application:
10/860,669 →
Methods and Apparatus for Efficient Synchronous Mimd Operations with Ivliw Pe-to-Pe Communication
Patent:
41,703 →
Application:
10/872,995 →
Methods and Apparatus for Dynamic Instruction Controlled Reconfigurable Register File
Patent:
7,398,347 →
Application:
10/890,625 →
Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response
Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing Dma Controller
Methods and Apparatus for Transforming, Loading, and Executing Super-Set Instructions
Patent:
7,493,474 →
Application:
10/985,264 →
Methods and Apparatus for Power Control in a Scalable Array of Processor Elements
Patent:
6,965,991 →
Application:
11/032,799 →
Coprocessor Instruction Loading from Port Register Based on Interrupt Vector Table Indication
Methods and Apparatus for Providing Data Transfer Control
Methods and Apparatus for Power Control in a Scalable Array of Processor Elements
Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
Application:
11/207,280 →
Publication:
US 2005/0289259
Methods and Apparatus for Efficient Vocoder Implementations
Coprocessor Processing Instructions in Turn from Multiple Instruction Ports Coupled to Respective Processors
Methods and Apparatus for Automated Generation of Abbreviated Instruction Set and Configurable Processor Architecture
Methods and Apparatus for Efficient Complex Long Multiplication and Covariance Matrix Implementation
Related Assignments
(18)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jun 30, 1997
From: PECHANEK, GERALD G.; KURAK, CHARLES W.
To: HOT CHIPS & SALSAS, INC.
Reel/Frame 008631/0427 →
Assignment of Assignor's Interest
Oct 10, 1997
From: PECHANEK, GERALD C.; PITSIANIS, NIKOS P.; BARRY, EDWIN F.; DRABENSTOFT, THOMAS L.
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 008775/0796 →
Assignment of Assignor's Interest
Dec 5, 1998
From: BARRY, EDWIN F.; PECHANEK, GERALD G.; DRABENSTOTT, THOMAS L.; WOLFF, EDWARD A.
To: BILLIONS OF OPERATIONS PER SCEOND INC.
Reel/Frame 009636/0304 →
Assignment of Assignor's Interest
Dec 24, 1998
From: PECHANEK, GERALD G.; REVILLA, JUAN G.
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 009666/0758 →
Assignment of Assignor's Interest
Dec 28, 1998
From: PECHANEK, GERALD G.; BARRY, EDWIN F.
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 009664/0711 →
Assignment of Assignor's Interest
Feb 1, 1999
From: PECHANEK, GERALD G.; DRABENSTOTT, THOMAS L.; REVILLA, JUAN GUILLERMO; STRUBE, DAVID CARL
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 009732/0459 →
Assignment of Assignor's Interest
Mar 11, 1999
From: PECHANEK, GERALD G.; REVILLA, JUAN GUILLERMO; BARRY, EDWIN F.
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 009812/0984 →
Assignment of Assignor's Interest
Mar 24, 1999
From: PECHANEK, GERALD G.; BARRY, EDWIN F.; REVILLA, JUAN GUILLERMO; LARSEN, LARRY D.
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 009846/0542 →
Assignment of Assignor's Interest
Apr 2, 1999
From: REVILLA, JUAN GUILLERMO; BARRY, EDWIN F.; MARCHAND, PATRICK RENE; PECHANEK, GERALD G.
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 009862/0820 →
Assignment of Assignor's Interest
Apr 26, 1999
From: DRABENSTOTT, THOMAS L.; PECHANEK, GERALD G.; BARRY, EDWIN F.; KURAK, CHARLES W. JR.
To: BILLIONS OF OPERATION PER SECOND INC.
Reel/Frame 009915/0155 →
Assignment of Assignor's Interest
May 7, 1999
From: BARRY, EDWIN F.; PECHANEK, GERALD G.; MARCH, PATRICK R.
To: BILLIONS OF OPERATIONS PER SECOND
Reel/Frame 009937/0092 →
Assignment of Assignor's Interest
Aug 4, 1999
From: PITSIANIS, NIKOS P.; PECHANEK, GERALD G.; RODRIGUEZ, RICARDO E.
To: BILLIONS OF OPERATIONS PER SECOND
Reel/Frame 010141/0716 →
Change of Name
May 18, 2001
From: BILLIONS OF OPERATIONS PER SECOND, INC.
To: BOPS, INC.
Reel/Frame 011812/0906 →
Change of Name
Jun 7, 2001
From: HOT CHIPS & SALSAS, INC.
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 011871/0202 →
Change of Name
Jun 7, 2001
From: BILLIONS OF OPERATIONS PER SECOND, INC.
To: BOPS, INC.
Reel/Frame 011871/0224 →
Change of Name
Jan 11, 2002
From: BILLIONS OF OPERATIONS PER SECOND, INC.
To: BOPS, INC.
Reel/Frame 012475/0750 →
Assignment of Assignor's Interest
Nov 20, 2003
From: BOPS, INC.
To: ALTERA CORPORATION
Reel/Frame 014683/0894 →
Assignment of Assignor's Interest
Nov 24, 2003
From: ALTERA CORPORATION
To: PTS CORPORATION
Reel/Frame 014683/0914 →