Methods and apparatus for power control in a scalable array of processor elements
Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.
1. A method for power control in a scalable pipelined array processor comprising the steps of:
controlling the execution of instructions in processing elements (PEs) and in a sequence processor (SP) by examining an S/P bit of each instruction;
masking off one or more PEs;
where a PE is masked off, allowing only PE communication DSU instructions to be decoded by the masked off PE, the masked off PE providing cluster switch control information in response to decoding a PE communication DSU instruction; and
maintaining all other execution units in masked off PEs in an inactive state to conserve power.
2. The method of claim 1 further comprising: keeping the PEs off when an SP-only instruction is executing; and gating an array clock off to the PEs.
3. A method for power control in a scalable pipelined array processor comprising:
configuring the scalable pipelined array as a 2×2 or smaller array processor, the scalable pipelined array processor having a plurality of processing elements (PEs), the plurality of PEs being connected to a cluster switch;
controlling the execution of instructions in the plurality of (PEs) and in a sequence processor (SP) by examining an S/P bit of each instruction;
masking off one or more of the plurality of PEs, with the masked off one or more of the plurality of PEs not executing any instructions, while the non-masked off PEs continue to communicate through the cluster switch without being effected by the masked off PEs; and
maintaining all execution units in masked off PEs in an inactive state to conserve power.
4. The method of claim 3 further comprising:
keeping the PEs off when an SP-only instruction is executing; and
gating an array clock off to the PEs.
5. A method for power control in a scalable pipelined array processor comprising:
controlling the execution of instructions in the plurality of PEs and in a sequence processor (SP);
masking off one or more PEs;
where a PE is masked off, allowing only PE communication DSU instructions to be decoded by the masked off PE, the masked off PE providing cluster switch control information in response to decoding a PE communication DSU instruction; and
maintaining all other execution units in masked off PEs in an inactive state to conserve power.
6. The method of claim 5 wherein the controlling step includes generating a HOLD_PIPE signal.