IP Library › Assignment 014683/0894
Patent Assignment
Reel/Frame 014683/0894

Assignment of Assignor's Interest

Recorded: 2003-11-20 Pages: 20
Assignor
BOPS, INC.
Executed: 2003-04-07
Assignee
ALTERA CORPORATION
101 INNOVATION DRIVE, SAN JOSE, CALIFORNIA, 95134
Covered Properties (59)
Hot Chips & Salsas Inc
Patent: 6,023,753 →
Application: 08/885,310 →
Method and Apparatus for Manifold Array Processing
Patent: 6,167,502 →
Application: 08/949,122 →
Merged Array Controller and Processing Element
Patent: 6,219,776 →
Application: 09/169,072 →
Methods and Apparatus for Dynamic Instruction Controlled Reconfiguration Register File with Extended Precision
Patent: 6,343,356 →
Application: 09/169,255 →
Methods and Apparatus for Manarray Pe-Pe Switch Control
Patent: 6,167,501 →
Application: 09/169,256 →
Methods and Apparatus for Efficient Synchronous Mimd Operations with Ivliw Pe-to-Pe Communication
Patent: 6,151,668 →
Application: 09/187,539 →
Methods and Apparatus for Dynamic Very Long Instruction Word Sub-Instruction Selection for Execution Time Parallelism in an Indirect Very Long Instruction Word Processor
Patent: 6,173,389 →
Application: 09/205,588 →
Methods and Appartus for Scalable Instruction Set Architecture with Dynamic Compact Instructions
Patent: 6,101,592 →
Application: 09/215,081 →
Methods and Apparatus to Dynamically Reconfigure the Instruction Pipeline of an Indirect Very Long Instruction Word Scalable Processor
Patent: 6,216,223 →
Application: 09/228,374 →
Methods and Apparatus to Support Conditional Execution in a Vliw-Based Array Processor with Subword Execution
Patent: 6,366,999 →
Application: 09/238,446 →
Register File Indexing Methods and Apparatus for Providing Indirect Control of Register Addressing in a Vliw Processor
Patent: 6,446,190 →
Application: 09/267,570 →
Manifold Array Processor
Patent: 6,338,129 →
Application: 09/323,609 →
Efficient Complex Multiplication and Fast Fourier Transform (Fft) Implementation on the Manarray Architecture
Patent: 6,839,728 →
Application: 09/337,839 →
Publication: US 2003/0088601
Methods and Apparatus for Instruction Addressing in Indirect Vliw Processors
Patent: 6,356,994 →
Application: 09/350,191 →
Methods and Apparatus for Abbreviated Instruction Sets Adaptable to Configurable Processor Architectures
Patent: 6,408,382 →
Application: 09/422,015 →
Methods and Apparatus for Improved Motion Estimation for Video Encoding
Patent: 6,697,427 →
Application: 09/432,705 →
Methods and Apparatus for Providing Data Transfer Control
Patent: 6,260,082 →
Application: 09/471,217 →
Methods and Apparatus for Providing Direct Memory Access Control
Patent: 6,256,683 →
Application: 09/472,372 →
Methods and apparatus for scalable instruction set architecture with dynamic compact instructions
Patent: 6,321,322 →
Application: 09/543,473 →
Accessing Tables in Memory Banks Using Load and Store Address Generators Sharing Store Read Port of Compute Register File Separated from Address Register File
Patent: 6,397,324 →
Application: 09/596,103 →
Methods and Apparatus for Establishing Port Priority Functions in a Vliw Processor
Patent: 6,654,870 →
Application: 09/598,084 →
Method and Apparatus for Providing Manifold Array (Manarray) Program Context Switch with Array Reconfigurable Control
Patent: 6,868,490 →
Application: 09/598,558 →
Methods and Apparatus for Initiating and Resysnchronizing Multi-Cycle Simd Instructions
Patent: 6,622,234 →
Application: 09/598,564 →
Specifying Different Type Generalized Event and Action Pair in a Processor
Patent: 6,735,690 →
Application: 09/598,566 →
Methods and Apparatus for Improved Efficiency in Pipeline Simulation and Emulation
Patent: 6,826,522 →
Application: 09/598,567 →
Constructing Database Representing Manifold Array Architecture Instruction Set for Use in Support Tool Code Creation
Patent: 6,748,517 →
Application: 09/599,980 →
Methods and apparatus for manarray PE-PE Switch control
Patent: 6,366,997 →
Application: 09/649,647 →
Methods and Apparatus for Efficient Synchronous Mimd Operations with Ivliw Pe-to-Pe Communication
Patent: 6,446,191 →
Application: 09/677,732 →
Methods and Apparatus for Manifold Array Processing
Patent: 6,470,441 →
Application: 09/707,209 →
Methods and Apparatus for Efficient Cosine Transform Implementations
Patent: 6,754,687 →
Application: 09/711,218 →
Methods and Apparatus for Dynamic Very Long Instruction Word Sub-Instruction Selection for Execution Time Parallelism in an Indirect Very Long Instruction Word Processor
Patent: 6,467,036 →
Application: 09/717,992 →
Methods and Apparatus for Loading a Very Long Instruction Word Memory
Patent: 6,704,857 →
Application: 09/747,056 →
Publication: US 2002/0002639
Merged Control / Process Element Processor for Executing Vliw Simplex Instructions with Sisd Control / Simd Process Mode Bit
Patent: 6,606,699 →
Application: 09/783,156 →
Publication: US 2001/0032303
Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response
Patent: 6,842,811 →
Application: 09/791,256 →
Publication: US 2001/0049763
Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing Dma Controller
Patent: 6,834,295 →
Application: 09/791,940 →
Publication: US 2002/0002640
Control processor dynamically loading shadow instruction register associated with memory entry of coprocessor in flexible coupling mode
Patent: 6,865,663 →
Application: 09/792,819 →
Publication: US 2001/0032305
Methods and Apparatus for Dynamic Instruction Controlled Reconfigurable Register File with Extended Precision
Patent: 6,430,677 →
Application: 09/796,037 →
Publication: US 2001/0011342
Methods and Apparatus to Dynamically Reconfigure the Instruction Pipeline of an Indirect Very Long Instruction Word Scalable Processor
Patent: 6,775,766 →
Application: 09/796,040 →
Publication: US 2003/0061473
Methods and Apparatus for Power Control in a Scalable Array of Processor Elements
Patent: 6,845,445 →
Application: 09/853,989 →
Publication: US 2002/0004916
Methods and Apparatus for Providing Direct Memory Access Control
Patent: 6,453,367 →
Application: 09/854,789 →
Publication: US 2001/0027499
Methods and Apparatus for Indirect Vliw Memory Allocation
Patent: 7,181,730 →
Application: 09/886,855 →
Publication: US 2002/0019910
Methods and Apparatus for Providing Data Transfer Control
Patent: 6,457,073 →
Application: 09/896,687 →
Publication: US 2002/0010814
Methods and Apparatus for Scalable Instruction Set Architecture with Dynamic Compact Instructions
Patent: 6,557,094 →
Application: 09/969,077 →
Publication: US 2002/0073299
Methods and Apparatus for Efficient Complex Long Multiplication and Covariance Matrix Implementation
Patent: 7,072,929 →
Application: 10/004,010 →
Publication: US 2002/0169813
Methods and Apparatus for Providing Improved Physical Designs and Routing with Reduced Capacitive Power Dissipation
Patent: 6,624,056 →
Application: 10/004,578 →
Publication: US 2002/0106878
Methods and Apparatus for Efficient Vocoder Implementations
Patent: 7,003,450 →
Application: 10/013,908 →
Publication: US 2002/0165709
Manifold Array Processor
Patent: 6,892,291 →
Application: 10/036,789 →
Publication: US 2002/0069343
Methods and Apparatus for Instruction Addressing in Indirect Vliw Processors
Patent: 6,581,152 →
Application: 10/073,782 →
Publication: US 2002/0078320
Methods and Apparatus for Manarray Pe-Pe Switch Control
Patent: 6,795,909 →
Application: 10/114,646 →
Publication: US 2002/0144082
Methods and Apparatus to Support Conditional Execution in a Vliw-Based Array Processor with Subword Execution
Patent: 6,760,831 →
Application: 10/114,652 →
Publication: US 2002/0178345
Methods and apparatus for generating functional test programs by traversing a finite state model of an instruction set architecture
Application: 10/116,221 →
Publication: US 2004/0078674
Methods and Apparatus for Automated Generation of Abbreviated Instruction Set and Configurable Processor Architecture
Patent: 7,028,286 →
Application: 10/119,660 →
Publication: US 2004/0015931
Methods and Apparatus for Pipelined Bus
Patent: 6,912,608 →
Application: 10/131,941 →
Publication: US 2003/0046462
Methods and Apparatus for Removing Compression Artifacts in Video Sequences
Patent: 6,993,191 →
Application: 10/136,651 →
Publication: US 2003/0020835
Methods and Apparatus for Dynamic Very Long Instruction Word Sub-Instruction Selection for Execution Time Parallelism in an Indirect Very Long Instruction Word Processor
Patent: 6,851,041 →
Application: 10/254,012 →
Publication: US 2003/0079109
Methods and Apparatus for Manifold Array Processing
Patent: 6,769,056 →
Application: 10/254,049 →
Publication: US 2003/0088754
Methods and Apparatus for Providing Data Transfer Control
Patent: 6,721,822 →
Application: 10/254,105 →
Publication: US 2003/0079065
Methods and apparatus for a bit rake instruction
Application: 10/282,919 →
Publication: US 2003/0105945
Methods and Apparatus for Multiple Stage Video Decoding
Patent: 7,181,070 →
Application: 10/282,925 →
Publication: US 2003/0161540
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jun 30, 1997
From: PECHANEK, GERALD G.; KURAK, CHARLES W.
To: HOT CHIPS & SALSAS, INC.
Reel/Frame 008631/0427 →
Assignment of Assignor's Interest Oct 10, 1997
From: PECHANEK, GERALD C.; PITSIANIS, NIKOS P.; BARRY, EDWIN F.; DRABENSTOFT, THOMAS L.
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 008775/0796 →
Assignment of Assignor's Interest Dec 5, 1998
From: BARRY, EDWIN F.; PECHANEK, GERALD G.; DRABENSTOTT, THOMAS L.; WOLFF, EDWARD A.
To: BILLIONS OF OPERATIONS PER SCEOND INC.
Reel/Frame 009636/0304 →
Assignment of Assignor's Interest Dec 24, 1998
From: PECHANEK, GERALD G.; REVILLA, JUAN G.
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 009666/0758 →
Assignment of Assignor's Interest Dec 28, 1998
From: PECHANEK, GERALD G.; BARRY, EDWIN F.
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 009664/0711 →
Assignment of Assignor's Interest Feb 1, 1999
From: PECHANEK, GERALD G.; DRABENSTOTT, THOMAS L.; REVILLA, JUAN GUILLERMO; STRUBE, DAVID CARL
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 009732/0459 →
Assignment of Assignor's Interest Mar 11, 1999
From: PECHANEK, GERALD G.; REVILLA, JUAN GUILLERMO; BARRY, EDWIN F.
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 009812/0984 →
Assignment of Assignor's Interest Mar 24, 1999
From: PECHANEK, GERALD G.; BARRY, EDWIN F.; REVILLA, JUAN GUILLERMO; LARSEN, LARRY D.
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 009846/0542 →
Assignment of Assignor's Interest Apr 2, 1999
From: REVILLA, JUAN GUILLERMO; BARRY, EDWIN F.; MARCHAND, PATRICK RENE; PECHANEK, GERALD G.
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 009862/0820 →
Assignment of Assignor's Interest Apr 26, 1999
From: DRABENSTOTT, THOMAS L.; PECHANEK, GERALD G.; BARRY, EDWIN F.; KURAK, CHARLES W. JR.
To: BILLIONS OF OPERATION PER SECOND INC.
Reel/Frame 009915/0155 →
Assignment of Assignor's Interest May 7, 1999
From: BARRY, EDWIN F.; PECHANEK, GERALD G.; MARCH, PATRICK R.
To: BILLIONS OF OPERATIONS PER SECOND
Reel/Frame 009937/0092 →
Assignment of Assignor's Interest Aug 4, 1999
From: PITSIANIS, NIKOS P.; PECHANEK, GERALD G.; RODRIGUEZ, RICARDO E.
To: BILLIONS OF OPERATIONS PER SECOND
Reel/Frame 010141/0716 →
Assignment of Assignor's Interest Oct 7, 1999
From: BARRY, EDWIN F.; PECHANEK, GERALD G.
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 010287/0808 →
Assignment of Assignor's Interest Dec 6, 1999
From: PECHANEK, GERALD G.; KURAK, CHARLES W. JR.; LARSEN, LARRY D.
To: BILLIONS OF OPERATIONS PER SECOND
Reel/Frame 010443/0031 →
Assignment of Assignor's Interest Jan 17, 2000
From: KURAK, CHARLES W. JR.; MOLLER, CHRISTIAN H. L.
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 010552/0705 →
Assignment of Assignor's Interest Feb 29, 2000
From: BARRY, EDWIN FRANK
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 010684/0666 →
Assignment of Assignor's Interest Mar 6, 2000
From: BARRY, EDWIN FRANK; WOLFF, EDWARD A.
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 010671/0140 →
Assignment of Assignor's Interest Oct 26, 2000
From: BARRY, EDWIN F.; PECHANEK, GERALD G.; STRUBE, DAVID CARL
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 011211/0611 →
Assignment of Assignor's Interest Oct 26, 2000
From: PECHANEK, GERALD G.; STRUBE, DAVID CARL; WOLFF, EDWARD A.; BARRY, EDWIN FRANK
To: BILLIONS OF OPERATINS PER SECOND, INC.
Reel/Frame 011218/0465 →
Assignment of Assignor's Interest Oct 26, 2000
From: BARRY, EDWIN F.; MARCHAND, PATRICK R.; PECHANEK, GERALD G.; KURAK, CHARLES W., JR.
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 011218/0454 →
Assignment of Assignor's Interest Oct 30, 2000
From: MOLLER, CHRISTIAN HENRIK LUJA; BUSBOOM, CARL DONALD; SCHNEIDER, DALE EDWARD
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 011214/0214 →
Assignment of Assignor's Interest Nov 2, 2000
From: BARRY, EDWIN FRANK; WOLFF, EDWARD A.; MARCHAND, PATRICK RENE; STRUBE, DAVID CARL
To: BILLIONS OF OPERATIONS PER SECOND, INC.
Reel/Frame 011235/0615 →
Change of Name May 14, 2001
From: BILLIONS OF OPERATIONS PER SECOND, INC.
To: BOPS, INC.
Reel/Frame 011564/0393 →
Change of Name May 18, 2001
From: BILLIONS OF OPERATIONS PER SECOND, INC.
To: BOPS, INC.
Reel/Frame 011812/0906 →
Change of Name Jun 7, 2001
From: BILLIONS OF OPERATIONS PER SECOND, INC.
To: BOPS, INC.
Reel/Frame 011871/0224 →