Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
1. An array processing system comprising:
a digital signal processor (DSP);
a direct memory access (DMA) controller;
a plurality of processing element (PE) local memories;
a direct memory access bus utilized by the DMA controller to access the plurality of PE local memories;
a system memory;
a system control bus (SCB) connected to the DMA controller; and
a system data bus (SDB) connecting the DMA controller and a plurality of devices, wherein the DMA controller transfers data between the plurality of devices on the SDB.
2. The array processing system of claim 1 wherein the system memory is on the SDB and the plurality of PE local memories are on a direct memory access bus as controlled by the DMA controller to move data between the system memory and the plurality of PE local memories.
3. The array processing system of claim 1 wherein the DSP functions as an SCB master and utilizes the SCB to program the DMA controller with read and write addresses and register values to initiate control operations and read status.
4. The array processing system of claim 1 further comprising a host processor connected to the SCB, and which both functions as an SCB master and utilizes the SCB to program the DMA controller with read and write addresses and register values to initiate control operations and read status.
5. The array processing system of claim 1 wherein the DMA controller further utilizes the SCB to send synchronization messages to other SCB bus slaves.
6. The array processing system of claim 5 wherein the other SCB bus slaves comprise DSP control registers or a host input/output block.
7. The array processing system of claim 5 further comprising a host processor connected to the SCB, and wherein the DSP or the host processor can poll registers in bus slaves on the SCB to receive status data from the DMA controller.
8. The array processing system of claim 1 wherein the DMA controller operates to perform write operations to slave addresses which are programmed to cause interrupt side effects to the DSP allowing DMA controller messages to be handled by interrupt service routines.