Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture
A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application. A hardware embodiment described herein allows application of the above mentioned high-entropy encoding technique in actual embedded processor using today's technology without posing significant strain on timing requirements.
1. A translation memory (TM) system comprising:
a byte addressable X-TM portion;
a byte addressable Y-TM portion;
an X-TM K-by-K byte-wide switch, wherein the X-TM K-by-K byte wide switch selects an X entry that is overlapped within K bytes of an accessed X-TM entry;
a Y-TM K-by-K byte-wide switch, wherein the Y-TM K-by-K byte wide switch selects a Y entry that is overlapped within K bytes of an accessed Y-TM entry;
an X-TM switch output latch holding the X entry as a latched X entry; and
a Y-TM switch output latch holding the Y entry as a latched Y entry, wherein overlapping X entries are stored in the X-TM to minimize the X-TM size, overlapping Y entries are stored in the Y-TM to minimize the Y-TM size, and the latched X entry and the latched Y entry are combined to create an instruction in a form suitable for execution on a core processor.
2. The TM system of claim 1 where K is 4 for a 32-bit 4 byte wide original instruction.
3. A translation memory (TM) system comprising:
a double ported read accessible byte addressable memory with one of the two read access ports associated with the X translation table entries and the other read access port associated with the Y translation table entries;
an X-TM port K-by-K byte-wide switch, wherein the X-TM K-by-K byte wide switch selects an X entry that is overlapped within K bytes of an accessed X-TM entry;
a Y-TM port K-by-K byte-wide switch, wherein the Y-TM K-by-K byte wide switch selects a Y entry that is overlapped within K bytes of an accessed Y-TM entry;
an X-TM port switch output latch holding the X entry as a latched X entry; and
a Y-TM port switch output latch holding the Y entry as a latched Y entry, wherein overlapping X entries are stored in the X-TM read port accessible portion to minimize the X-TM size, overlapping Y entries are stored in the Y-TM read port accessible portion to minimize the Y-TM size, and the latched X entry and the latched Y entry are combined to create an instruction in a form suitable for execution on a core processor.
4. The TM system of claim 3 where K is 4 for a 32-bit 4 byte wide original instruction.
5. The TM system of claim 3 where uncompressed instructions can be stored in the memory.
6. The TM system of claim 3 , wherein the memory is configured as an instruction cache-like structure.