IP Library Granted Patent US 7,151,693
Granted Patent B2
US 7,151,693 · App. 11/101,415 · Granted Dec 19, 2006

Method of writing data to a non-volatile semiconductor memory

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Quick Facts
Patent No.
US 7,151,693
App. No.
11/101,415
Granted
Dec 19, 2006
Kind
B2
Abstract

A method of writing data into a non-volatile semiconductor memory having a plurality of memory cells in which a word line is shared by memory cells and a bit line is shared by adjacent memory cells, the method including writing the data into memory cells connected to the same word line sequentially from a memory cell at one end to a memory cell at another end.

Claims (12)

1. A method of writing data into a non-volatile semiconductor memory having a plurality of memory cells in which a word line is shared by memory cells and a bit line is shared by adjacent memory cells,

the method comprising writing the data into memory cells connected to the same word line sequentially from a memory cell at one end to a memory cell at another end.

2. A method according to claim 1 , wherein, in the memory cells connected to the same word line, a bit line on one side of the memory cell at said one end functions as a source.

3. A method according to claim 1 , wherein the data is written into the memory cells by channel hot electrons.

4. A method of writing data into a non-volatile semiconductor memory having a plurality of memory cells in which a word line is shared by memory cells and a bit line is shared by adjacent memory cells connected to the same word line, the method comprising writing the data into memory cells connected to the same word line sequentially from a memory cell at one end to a memory cell at another end.

5. A method of writing data to a cell row of a non-volatile volatile semiconductor memory, the cell row comprising first through n-th memory cells connected to the same word line, the first through n-th memory cells being connected in series between a source line and an n-th bit line and having respective channel directions that extend in the row direction, wherein first through (n−1)-th bit lines are respectively connected to a corresponding one of the nodes between each pair of the series-connected memory cells, the method comprising:

applying voltages to the source line and the bit lines so as to write data sequentially to the first through n-th memory cells of the cell row.

6. The method according to claim 5 , wherein

data is written to the first memory cell by applying a first voltage to the source line and a second voltage different than the first voltage to bit lines 1 through n; and

data is written to the remaining memory cells by sequentially changing the voltage applied to bit lines 1 through n−1 from the second voltage to the first voltage.

7. The method according to claim 5 , wherein the voltages applied to the source line and the bit lines to write data generate channel hot electrons.

8. The method according to claim 5 , wherein the bit lines comprise diffusion regions.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 035120 FRAME: 0878. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 5, 2015
From: INTELLECTUAL PROPERTIES I KFT.
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 035837/0619 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2015
From: INTELLECTUAL PROPERTIES I KFT.
To: SAMSUNG ELECTRONICS CO., LTD
Reel/Frame 035120/0878 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2011
From: SHARP KABUSHIKI KAISHA
To: INTELLECTUAL PROPERTIES I KFT.
Reel/Frame 027387/0650 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2011
From: YAMAUCHI, YOSHIMITSU
To: SHARP KABUSHIKI KAISHA
Reel/Frame 027214/0830 →