Low locality-of-reference support in a multi-level cache hierachy
View Patent ↗A processor includes a multi-level cache hierarchy where locality information property such as a Low Locality of Reference (LLR) property is associated with a cache line. The LLR cache line retains the locality information and may move back and forth within the cache hierarchy until evicted from the outer-most level of the cache hierarchy.
1. A method to cache information in a multi-level cache memory hierarchy, comprising: evicting a cache line from a first level of the cache memory hierarchy to a second level of the cache memory hierarchy; and transmitting locality information as a low locality of reference (LLR) bit stored with the cache line in the first level to the second level for storage with the cache line to distinguish the cache line from other cache lines with different stored locality information, wherein the locality information indicates that the probability that the cache line will be used in a predetermined amount of time in the future is less than that of typical cache line data, wherein the second level of the cache memory uses the locality information in replacement and allocation decisions for the second level of the cache memory.
2. The method of claim 1 , wherein obtaining locality information includes using a page table to obtain the locality information.
3. The method of claim 1 , wherein the locality information is included in a tag field associated with the cache line.
4. The method of claim 1 , wherein the first level of the cache memory hierarchy examines the locality information to determine whether to transfer the cache line to the second level of the cache memory hierarchy.
5. An article comprising a machine-accessible medium having associated data, wherein the data, when accessed, results in a machine performing: evicting a cache line from a first level of a cache memory hierarchy to a second level of the cache memory hierarchy; and transmitting locality information assigned for storage with the cache line as a low locality of reference (LLR) bit in the second level of the cache memory hierarchy, wherein the locality information indicates that the probability that the cache line will be used in a predetermined amount of time in the future is less than that of typical data in a cache line, wherein the second level of the cache memory uses the locality information in replacement and allocation decisions for the second level of the cache memory.
6. A system comprising: a multi-level cache memory; and a processor to evict a cache line from a first level to a second level of the multi-level cache memory and to transmit locality information as a low locality of reference (LLR) bit stored with the cache line in the second level of the cache memory, wherein the locality information indicates that the probability that the cache line will be used in a predetermined amount of time in the future is less than that of typical data in a cache line, wherein the second level of the cache memory uses the locality information in replacement and allocation decisions for the second level of the cache memory.
7. A processor having multi-level cache hierarchy comprising: a first level cache where cache lines have an associated Low Locality of Reference (LLR) bit to indicate a probability that the cache line will be used within a predetermined time period, wherein the LLR bit indicates that the probability that the cache line will be used in a predetermined amount of time in the future is less than that of typical data in a cache line; and an outer level cache to receive a cache line evicted from the first level cache and a decision based on a stored LLR bit transferred with the evicted cache line determines an action to take with the evicted cache line, wherein the outer level of the cache memory uses the LLR bit in replacement and allocation decisions for the outer level of the cache memory.
8. The processor of claim 7 wherein the outer level cache has an LLR line stored in the set that is replaced by the LLR line from the first cache.
9. The processor of claim 7 wherein the outer level cache does not have an LLR line stored in the set and a replacement is not allowed.
10. The processor of claim 7 wherein the cache line retains the LLR bit and may move back and forth within the cache hierarchy until evicted from the outer level of the cache hierarchy.