Layout technique for matched resistors on an integrated circuit substrate
View Patent ↗Provided a method of reducing impedance variations in an electrical circuit structured and arranged for placement on an integrated circuit (IC) substrate. The method includes forming sets of parallel connected resistors, each set corresponding to one of the impedance devices on the IC. Each set also includes two or more parallel resistor paths, each resistor path including two or more cascaded resistors and has a total impedance value substantially equal to the predetermined impedance value of its corresponding impedance device. Finally, the method includes configuring the sets of parallel resistor paths to form an interdigital structure across the substrate when the electrical circuit is placed on the IC.
1. A method for matching resistor impedances in an electrical circuit configured for placement on an integrated circuit substrate, the method comprising:
determining desired resistor values to be associated with the circuit; and
defining interdigital structures to be formed across the substrate when the circuit is placed thereon, the interdigital structures being formed when paths of interconnected resistors split at one point on the substrate and recombine at another point, the paths of interconnected resistors being representative of the desired resistor values.
2. The apparatus of claim 1 , wherein the electrical circuit comprises a programmable gain amplifier (PGA).
3. The apparatus of claim 2 , wherein the PGA is a differential amplifier.
4. The apparatus of claim 3 , wherein the circuit is formed in CMOS.