Semiconductor integrated circuit device with reduced leakage current
View Patent ↗The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
1. A semiconductor integrated circuit device comprising:
a plurality of static type memory cells respectively having a pair of load P-channel transistor and a driver N-channel transistor, an insulating layer for use in a gate of either of the load P-channel transistor or the driver N-channel transistor has a thickness of 4 nm or less;
a power line being connected to source electrodes of each of the load P-channel transistors, through which power is supplied to each of the load P-channel transistors; and
a source line being connected to source electrodes of each of the driver N-channel transistors;
wherein a voltage difference between a voltage on the power line and another voltage on the source line is controlled to be set at a first value in an operating mode with a first current flowing from the load P-channel transistor to ground through the driver N-channel transistor, and wherein the voltage difference is further controlled to be set at a second value lower than the first value in a standby mode with another current at least one digit less than the first current.
2. The semiconductor integrated circuit device according to claim 1 , wherein the plurality of memory cells are selected to perform read or write data in the operating mode.
3. The semiconductor integrated circuit device according to claim 1 wherein the operating mode and the standby mode are switched on a selecting signal.
4. A semiconductor integrated circuit device comprising:
a plurality of static type memory cells respectively having a pair of load P-channel transistor and a driver N-channel transistor, an insulating layer for use in a gate of either of the load P-channel transistor or the driver N-channel transistor has a thickness of 4 nm or less;
a power line being connected to source electrodes of each of the load P-channel transistors, through which power is supplied to each of the load P-channel transistors; and
a source line being connected to source electrodes of each of the driver N-channel transistors;
wherein a voltage of the power line is controlled to be set at a first potential value in both an operating mode with a first current flowing from the load P-channel transistor to ground through the driver N-channel transistor and a standby mode with another current at least one digit less than the first current;
wherein a voltage of the source line is controlled to be set at a second potential value higher than the first potential value in the operating mode, and set at a third potential value higher than the second potential value in the standby mode; and
wherein a substrate voltage of the drive N-channel transistor is controlled to be set at the second value in both the operating mode and the standby mode.
5. The semiconductor integrated circuit device according to claim 4 , wherein the plurality of memory cells are selected to perform read or write data in the operating mode.
6. The semiconductor integrated circuit device according to claim 4 , wherein the operating mode and the standby mode are switched on a selecting signal.