Technique for improving negative potential immunity of an integrated circuit
View Patent ↗An integrated circuit (IC) with negative potential protection includes at least one double-diffused metal-oxide semiconductor (DMOS) cell formed in a first-type epitaxial pocket, which is formed in a second-type substrate. The IC also includes a second-type+ isolation ring formed in the substrate to isolate the first-type epitaxial pocket and a first-type+ ring formed through the first-type epitaxial pocket between the second-type+ isolation ring and the DMOS cell.
1. An integrated circuit having negative potential protection, comprising:
a first double-diffused metal-oxide semiconductor (DMOS) cell formed in a first-type epitaxial pocket, wherein the first-type epitaxial pocket is formed in a second-type substrate;
a second-type+ isolation ring formed in the substrate to isolate the first-type epitaxial pocket;
one of a first-type+ ring or an isolation trench formed through the first-type epitaxial pocket between the second-type+ isolation ring and the first DMOS cell;
a second DMOS cell formed in the first-type epitaxial pocket, wherein the first and second DMOS cells have a common drain and a source of the second DMOS cell is coupled to one of the isolation ring and the substrate; and
a comparator including an output, a first input and a second input, wherein an output of the comparator is coupled to a gate of the second DMOS cell, and wherein the first input of the comparator receives a reference signal and the second input of the comparator is coupled to the common drain, where the comparator provides a turn-on signal to the gate of the second DMOS cell when a signal at the second input is below the reference signal, and where the turn-on signal causes the second DMOS cell to conduct shorting a base-emitter junction of a parasitic NPN transistor.
2. The integrated circuit of claim 1 , wherein the first-type+ ring reduces a forward current gain of a parasitic PNP transistor.
3. The integrated circuit of claim 1 , wherein the first-type+ ring is an N-type+ ring.
4. The integrated circuit of claim 3 , wherein the first-type epitaxial pocket is an N-type epitaxial pocket.
5. The integrated circuit of claim 4 , wherein the second-type substrate is a P-type substrate.
6. The integrated circuit of claim 5 , wherein the second-type+ isolation ring is a P-type+ isolation ring.
7. The device of claim 1 , further comprising:
a plurality of N-type+ regions formed in the substrate on either side of a P-type body of the DMOS cell.
8. The integrated circuit of claim 1 , further comprising:
a pass transistor including a gate, a drain and a source, wherein the drain of the pass transistor is coupled to the common drain and the source of the pass transistor is coupled to the second input of the comparator, and wherein the gate of the pass transistor is controlled to couple the drain of the first DMOS cell to the second input of the comparator when a voltage at the drain of the first DMOS cell is below a predetermined level.
9. An integrated circuit having negative potential protection, comprising:
at least one double-diffused metal-oxide semiconductor (DMOS) cell formed in an N-type epitaxial pocket, wherein the N-type epitaxial pocket is formed in a P-type substrate;
a P-type+ isolation ring formed in the substrate to isolate the N-type epitaxial pocket;
an N-type+ ring formed through the N-type epitaxial pocket between the P-type+ isolation ring and the DMOS cell;
a second DMOS cell formed in the N-type epitaxial pocket, wherein the first and second DMOS cells have a common drain and a source of the second DMOS cell is coupled to one of the isolation ring and the substrate; and
a comparator including an output, a first input and a second input, wherein an output of the comparator is coupled to a gate of the second DMOS cell, and wherein the first input of the comparator receives a reference signal and the second input of the comparator is coupled to the common drain, where the comparator provides a turn-on signal to the gate of the second DMOS cell when a signal at the second input is below the reference signal, and where the turn-on signal causes the second DMOS cell to conduct shorting a base-emitter junction of a parasitic NPN transistor.
10. The integrated circuit of claim 9 , wherein the N-type+ ring reduces a forward current gain of a parasitic PNP transistor.
11. The device of claim 9 , further comprising:
a plurality of N-type+ regions formed in the substrate on either side of the P-type body of the DMOS cell.
12. The integrated circuit of claim 9 , further comprising:
a pass transistor including a gate, a drain and a source, wherein the drain of the pass transistor is coupled to the common drain and the source of the pass transistor is coupled to the second input of the comparator, and wherein the gate of the pass transistor is controlled to couple the drain of the first DMOS cell to the second input of the comparator when a voltage at the drain of the first DMOS cell is below a predetermined level.
13. An integrated circuit having negative potential protection, comprising:
a first double-diffused metal-oxide semiconductor (DMOS) cell formed in a first-type epitaxial pocket, wherein the first-type epitaxial pocket is formed in a second-type substrate;
a second-type+ isolation ring formed in the substrate to isolate the first-type epitaxial pocket;
a second DMOS cell formed in the first-type epitaxial pocket, wherein the first and second DMOS cells have a common drain and a source of the second DMOS cell is coupled to one of the isolation ring and the substrate; and
a comparator including an output, a first input and a second input, wherein an output of the comparator is coupled to a gate of the second DMOS cell, and wherein the first input of the comparator receives a reference signal and the second input of the comparator is coupled to the common drain, where the comparator provides a turn-on signal to the gate of the second DMOS cell when a signal at the second input is below the reference signal, and where the turn-on signal causes the second DMOS cell to conduct shorting a base-emitter junction of a parasitic NPN transistor.
14. The integrated circuit of claim 13 , further comprising:
a first-type+ ring formed through the first-type epitaxial pocket between the second-type+ isolation ring and the first DMOS cell.
15. The integrated circuit of claim 14 , wherein the first-type+ ring reduces a forward current gain of a parasitic PNP transistor.
16. The device of claim 13 , further comprising:
a plurality of N-type+ regions formed in the substrate on either side of the P-type body of the DMOS cell.
17. The integrated circuit of claim 13 , further comprising:
a pass transistor including a gate, a drain and a source, wherein the drain of the pass transistor is coupled to the common drain and the source of the pass transistor is coupled to the second input of the comparator, and wherein the gate of the pass transistor is controlled to couple the drain of the first DMOS cell to the second input of the comparator when a voltage at the drain of the first DMOS cell is below a predetermined level.