Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device
View Patent ↗A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
1. A method of manufacturing a semiconductor device, comprising steps of:
(a) forming first conductor patterns over a nonvolatile memory cell forming region of a semiconductor substrate and a peripheral circuit region of said semiconductor substrate such that said first conductor patterns define an active region of an MISFET in said peripheral circuit region;
(b) forming grooves into said semiconductor substrate, in self-alignment with said first conductor patterns, at said nonvolatile memory cell forming region and at said peripheral circuit region such that said grooves serve as an element isolation region in said nonvolatile memory cell forming region and at said peripheral circuit region;
(c) filling a first insulating film in said grooves by polishing an insulating film deposited over said grooves;
(d) after said step (c), under a condition that said first conductor patterns remain, forming second conductor patterns over said first conductor patterns;
(e) forming a conductive film over said second conductor patterns; and
(f) patterning said conductive film, said second conductor patterns and said first conductor patterns in said nonvolatile memory cell forming region and in said peripheral circuit region,
wherein, in said step (f), said conductive film of said nonvolatile memory cell forming region is patterned to form a control gate electrode of a nonvolatile memory cell,
wherein, in said step (f), said second conductor patterns and said first conductor patterns of said nonvolatile memory cell forming region are patterned to form a floating gate electrode of said nonvolatile memory cell,
wherein, in said step (f), said second conductor patterns and said first conductor patterns of said peripheral circuit region are patterned to form a gate electrode structure of said MISFET of said peripheral circuit region,
wherein, in said step (a), said first conductor patterns include a conductive layer and an insulating layer formed over said conductive layer,
wherein, in said step (c), said insulating layer functions as a stopper layer in polishing said insulating film, and
wherein before said step (d), said insulating layer is removed.
2. A method of manufacturing a semiconductor device according to claim 1 , wherein, in said step (f), said conductive film of said peripheral circuit region is patterned.
3. A method of manufacturing a semiconductor device according to claim 1 , wherein, in step (b), the grooves at said nonvolatile memory cell forming region and at said peripheral circuit region are formed simultaneously in self-alignment with said first conductor patterns.
4. A method of manufacturing a semiconductor device according to claim 1 , wherein, in the step (a), side wall spacers are formed as side walls of the first conductor patterns, and wherein, in the step (b), the grooves are formed in self-alignment with said first conductor patterns including said side walls spacers.
5. A method of manufacturing a semiconductor device, comprising steps of:
(a) forming first conductor patterns over a nonvolatile memory cell forming region of a semiconductor substrate and a peripheral circuit region of said semiconductor substrate such that said first conductor patterns define an active region of an MISFET in said peripheral circuit region;
(b) forming grooves into said semiconductor substrate, in self-alignment with said first conductor patterns, at said nonvolatile memory cell forming region and at said peripheral circuit region such that said grooves serve as an element isolation region in said nonvolatile memory cell forming region and at said peripheral circuit region;
(c) filling a first insulating film in said grooves by polishing an insulating film deposited over said grooves;
(d) after said step (c), under a condition that said first conductor patterns remain, forming second conductor patterns over said first conductor patterns;
(e) forming a conductive film over said second conductor patterns; and
(f) patterning said conductive film, said second conductor patterns and said first conductor patterns in said nonvolatile memory cell forming region and in said peripheral circuit region,
wherein, in said step (f), said conductive film of said nonvolatile memory cell forming region is patterned to form a control gate electrode of a nonvolatile memory cell,
wherein, in said step (f), said second conductor patterns and said first conductor patterns of said nonvolatile memory cell forming region are patterned to form a floating gate electrode of said nonvolatile memory cell,
wherein, in said step (f), said conductive film of said peripheral circuit region is patterned to form a gate electrode structure of said MISFET of said peripheral circuit region,
wherein, in said step (a), said first conductor patterns include a conductive layer and an insulating layer formed over said conductive layer,
wherein, in said step (c), said insulating layer functions as a stopper layer in polishing said insulating film, and
wherein before said step (d), said insulating layer is removed.
6. A method of manufacturing a semiconductor device according to claim 5 , wherein, before said step (e), said second conductor patterns and said first conductor patterns of said peripheral circuit region are removed in said peripheral circuit region.
7. A method of manufacturing a semiconductor device according to claim 5 , wherein, in said step (f), said conductive film, said second conductor patterns and said first conductor patterns of said peripheral circuit region are patterned to form said gate electrode structure of said MISFET of said peripheral circuit region.
8. A method of manufacturing a semiconductor device according to claim 5 , wherein, in step (b), the grooves at said nonvolatile memory cell forming region and at said peripheral circuit region are formed simultaneously in self-alignment with said first conductor patterns.
9. A method of manufacturing a semiconductor device according to claim 5 , wherein, in the step (a), side wall spacers are formed as side walls of the first conductor patterns, and wherein, in the step (b), the grooves are formed in self-alignment with said first conductor patterns including said side walls spacers.
10. A method of manufacturing a semiconductor device, comprising steps of:
(a) forming first conductor patterns over a nonvolatile memory cell forming region of a semiconductor substrate and a peripheral circuit region of said semiconductor substrate such that said first conductor patterns define an active region of an MISFET in said peripheral circuit region;
(b) forming grooves into said semiconductor substrate, in self-alignment with said first conductor patterns, at said nonvolatile memory cell forming region and at said peripheral circuit region such that said grooves serve as an element isolation region in said nonvolatile memory cell forming region and at said peripheral circuit region;
(c) filling a first insulating film in said grooves by polishing an insulating film deposited over said grooves;
(d) after said step(c), under a condition that said first conductor patterns remain, forming a conductive film over said first conductor patterns; and
(e) patterning said conductive film and said first conductor patterns in said nonvolatile memory cell forming region and in said peripheral circuit region,
wherein, in said step (e), said conductive film of said nonvolatile memory cell forming region is patterned to form a control gate electrode of a nonvolatile memory cell,
wherein, in said step (e), said first conductor patterns of said nonvolatile memory cell forming region are patterned to form a floating gate electrode of said nonvolatile memory cell,
wherein, in said step (e), said first conductor patterns of said peripheral circuit region are patterned to form a gate electrode structure of said MISFET of said peripheral circuit region,
wherein, in said step (a), said first conductor patterns include a conductive layer and an insulating layer formed over said conductive layer,
wherein, in said step (c), said insulating layer functions as a stopper layer in polishing said insulating film, and
wherein before said step (d), said insulating layer is removed.
11. A method of manufacturing a semiconductor device according to claim 10 , wherein, in said step (e), said conductive film of said peripheral circuit region is patterned.
12. A method of manufacturing a semiconductor device according to claim 10 , wherein, in step (b), the grooves at said nonvolatile memory cell forming region and at said peripheral circuit region are formed simultaneously in self-alignment with said first conductor patterns.
13. A method of manufacturing a semiconductor device according to claim 10 , wherein, in the step (a), side wall spacers are formed as side walls of the first conductor patterns, and wherein, in the step (b), the grooves are formed in self-alignment with said first conductor patterns including said side walls spacers.
14. A method of manufacturing a semiconductor device, comprising steps of:
(a) forming first conductor patterns over a nonvolatile memory cell forming region of a semiconductor substrate and a peripheral circuit region of said semiconductor substrate such that said first conductor patterns define an active region of an MISFET in said peripheral circuit region;
(b) forming grooves into said semiconductor substrate, in self-alignment with said first conductor patterns, at said nonvolatile memory cell forming region and at said peripheral circuit region such that said grooves serve as an element isolation region in said nonvolatile memory cell forming region and at said peripheral circuit region;
(c) filling a first insulating film in said grooves by polishing an insulating film deposited over said grooves;
(d) after said step (c), under a condition that said first conductor patterns remain, forming a conductive film over said first conductor patterns; and
(e) patterning said conductive film and said first conductor patterns in said nonvolatile memory cell forming region and in said peripheral circuit region,
wherein, in said step (e), said conductive film of said nonvolatile memory cell forming region is patterned to form a control gate electrode of a nonvolatile memory cell,
wherein, in said step (e), said first conductor patterns of said nonvolatile memory cell forming region are patterned to form a floating gate electrode of said nonvolatile memory cell,
wherein, in said step (e), said conductive film of said peripheral circuit region is patterned to form a gate electrode structure of said MISFET of said peripheral circuit region,
wherein, in said step (a), said first conductor patterns include a conductive layer and an insulating layer formed over said conductive layer,
wherein, in said step (c), said insulating layer functions as a stopper layer in polishing said insulating film, and
wherein before said step (d), said insulating layer is removed.
15. A method of manufacturing a semiconductor device according to claim 14 , wherein, before said step (d), said first conductor patterns of said peripheral circuit region are removed in said peripheral circuit region.
16. A method of manufacturing a semiconductor device according to claim 14 , wherein, in said step (e), said conductive film and said first conductor patterns of said peripheral circuit region are patterned to form said gate electrode structure of said MISFET of said peripheral circuit region.
17. A method of manufacturing a semiconductor device according to claim 14 , wherein, in step (b), the grooves at said nonvolatile memory cell forming region and at said peripheral circuit region are formed simultaneously in self-alignment with said first conductor patterns.
18. A method of manufacturing a semiconductor device according to claim 14 , wherein, in the step (a), side wall spacers are formed as side walls of the first conductor patterns, and wherein, in the step (b), the grooves are formed in self-alignment with said first conductor patterns including said side walls spacers.