Void free interlayer dielectric

1. A method of manufacturing a memory device, the method comprising:

forming a plurality of memory cells, said forming including:

forming a first dielectric layer over a substrate of the memory device;

forming a charge storage element over the first dielectric layer;

forming a second dielectric layer over the charge storage element;

forming a control gate over the second dielectric layer;

depositing a dielectric layer to a thickness ranging from about 50 Å to about 500 Å over the control gate of each of the plurality of memory cells and the substrate,

depositing the dielectric layer including:

using an atomic layer deposition process to deposit the dielectric layer to the thickness ranging from about 50 Å to about 500 Å,

the dielectric layer, deposited using the atomic layer deposition process, filling spaces between adjacent memory cells of the plurality of memory cells, and

the dielectric layer, deposited using the atomic layer deposition process, having a substantially uniform thickness that prevents re-entrant angles,

the dielectric layer comprising a silicon nitride; and

depositing an interlayer dielectric over the dielectric layer,

the interlayer dielectric comprising boro-phosphosilicate glass and being deposited to a thickness ranging from about 2,000 Å to about 11,000 Å,

the interlayer dielectric being deposited to fill, based on the substantially uniform thickness that prevents the re-entrant angles, the spaces between the adjacent memory cells,

voids, in the interlayer dielectric, being eliminated based on the interlayer dielectric being deposited to fill the spaces between the adjacent memory cells.

2. The method of claim 1 , where the interlayer dielectric has a thickness ranging from about 5,000 Å to about 11,000 Å.

3. The method of claim 1 , where the dielectric layer acts as a liner for the interlayer dielectric.

4. The method of claim 3 , where the dielectric layer contacts at least a portion of the substrate.

5. The method of claim 1 , where the dielectric layer and the interlayer dielectric form an interlayer dielectric that is:

located closest to the substrate, and

formed without voids.

6. The method of claim 1 , further comprising:

forming spacers adjacent side surfaces of:

the first dielectric layer of each of the adjacent memory cells,

the charge storage element of each of the adjacent memory cells,

the second dielectric layer of each of the adjacent memory cells, and

the control gate of each of the adjacent memory cells,

where the spacers contact at least a portion of the side surfaces of:

the first dielectric layer of each of the adjacent memory cells,

the charge storage element of each of the adjacent memory cells,

the second dielectric layer of each of the adjacent memory cells, and

the control gate of each of the adjacent memory cells.

7. The method of claim 6 , where the control gate includes germanium or silicon-germanium, and

where depositing the dielectric layer further includes:

depositing the dielectric layer over the spacers,

where the dielectric layer contacts:

at least a portion of the spacers, and

an upper surface of the germanium or the silicon-germanium included in the control gate.

8. The method of claim 1 , further comprising:

planarizing the interlayer dielectric;

forming a conductive interconnect line over the interlayer dielectric, after planarizing the interlayer dielectric; and

forming another interlayer dielectric over the conductive interconnect line.

9. The method of claim 8 , further comprising:

forming a contact hole in the dielectric layer and the interlayer dielectric after planarizing the interlayer dielectric and before forming the conductive interconnect line over the interlayer dielectric; and

depositing a metal layer in the contact hole,

the metal layer filling the contact hole and corresponding to a contact to a source region or a drain region of the substrate,

the conductive interconnect line being formed over the interlayer dielectric and over the metal layer deposited in the contact hole.

10. A method of manufacturing a non-volatile memory device, the method comprising:

forming a plurality of memory cells on a substrate of the memory device;

depositing a dielectric layer over the plurality of memory cells and over the substrate to a thickness ranging from about 50 Å to about 500 Å,

the dielectric layer comprising silicon dioxide,

depositing the dielectric layer including:

using an atomic layer deposition process to deposit the dielectric layer, to the thickness ranging from about 50 Å to about 500 Å,

the dielectric layer, deposited using the atomic layer deposition process, filling spaces between adjacent memory cells of the plurality of memory cells, and

the dielectric layer, deposited using the atomic layer deposition process, having a substantially uniform thickness that prevents re-entrant angles; and

depositing an interlayer dielectric having a thickness ranging from about 2,000 Å to about 11,000 Å, over the dielectric layer,

the interlayer dielectric including a boro-phosphosilicate glass material or a phosphosilicate glass material,

the interlayer dielectric being deposited to fill, based on the substantially uniform thickness that prevents the re-entrant angles, the spaces between the adjacent memory cells,

voids, in the interlayer dielectric, being eliminated based on the interlayer dielectric being deposited to fill the spaces between the adjacent memory cells.

11. The method of claim 10 , further comprising:

forming spacers adjacent side surfaces of at least one of the plurality of memory cells,

where the spacers contact at least a portion of the side surfaces of the at least one of the plurality of memory cells, and

where depositing the dielectric layer further comprises:

depositing the dielectric layer over the spacers,

where the dielectric layer contacts at least a portion of:

the spacers, and

a top surface of the at least one of the plurality of memory cells.

12. The method of claim 10 , further comprising:

planarizing the interlayer dielectric; and

forming a conductive line over the interlayer dielectric, after planarizing the interlayer dielectric.

13. The method of claim 12 , further comprising:

forming another interlayer dielectric over the conductive line.

14. The method of claim 10 , where a thickness, of the interlayer dielectric, ranges from about 5,000 Å to about 11,000 Å.

15. The method of claim 10 , where the dielectric layer acts as a liner for the interlayer dielectric.

16. The method of claim 10 , where the dielectric layer contacts at least a portion of the substrate.

17. The method of claim 10 , where the dielectric layer and the interlayer dielectric form an interlayer dielectric that is:

located closest to the substrate, and

formed without voids.