Patent Assignment
Reel/Frame 042416/0448
Assignment of Assignor's Interest
Recorded: 2017-05-17
Received: 2017-05-17
Pages: 7
Assignor
ADVANCED MICRO DEVICES, INC.
Executed: 2017-05-09
Assignee
SPANSION LLC
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
Covered Properties
(34)
Contacts for Semiconductor Devices
Application:
14/059,077 →
Method and Apparatus for Protection Against Process-Induced Charging
Application:
13/866,915 →
Void Free Interlayer Dielectric
Application:
13/732,096 →
Etch Stop Layer for Memory Cell Reliability Improvement
Application:
13/617,291 →
Damascene Metal-Insulator-Metal (Mim) Device with Improved Scaleability
Application:
13/529,284 →
Memory Device Having Trapezoidal Bitlines and Method of Fabricating Same
Application:
13/357,252 →
Buried Silicide Local Interconnect with Sidewall Spacers and Method for Making the Same
Application:
13/281,491 →
Gap-Filling with Uniform Properties
Application:
12/982,364 →
Buried Silicide Local Interconnect with Sidewall Spacers and Method for Making the Same
Application:
12/843,131 →
Memory Device Etch Methods
Application:
12/688,477 →
Integrated Circuit System with Memory System
Application:
11/958,646 →
Methods of Forming Silicides of Different Thicknesses on Different Structures
Application:
11/748,743 →
Semiconductor Memory Device
Application:
11/656,437 →
Semiconductor Memory Device
Application:
11/656,438 →
Memory Device Etch Methods
Application:
11/616,085 →
Method and Apparatus for Protection Against Process-Induced Charging
Application:
11/614,053 →
Contacts for Semiconductor Devices
Application:
11/551,532 →
Memory Cell System with Charge Trap
Application:
11/539,984 →
Damascene Metal-Insulator-Metal (Mim) Device with Improved Scaleability
Application:
11/521,204 →
Integrated Circuit Memory System Employing Silicon Rich Layers
Application:
11/461,131 →
Gap-Filling with Uniform Properties
Application:
11/408,086 →
Void Free Interlayer Dielectric
Application:
11/201,378 →
Interlayer Dielectric for Charge Loss Improvement
Application:
11/147,208 →
Buried Silicide Local Interconnect with Sidewall Spacers and Method for Making the Same
Application:
11/136,569 →
Aggressive Cleaning Process for Semiconductor Device Contact Formation
Application:
11/128,391 →
Void Free Interlayer Dielectric
Application:
11/109,719 →
Disposable Hard Mask for Forming Bit Lines
Application:
11/100,563 →
Ultraviolet Radiation Blocking Interlayer Dielectric
Application:
11/091,519 →
Semiconductor Memory Device
Application:
11/066,567 →
Memory Cell and Method of Making the Memory Cell
Application:
11/063,138 →
Method for Controlling Poly 1 Thickness and Uniformity in a Memory Array Fabrication Process
Application:
11/035,188 →
Memory Device Having Trapezoidal Bitlines and Method of Fabricating Same
Application:
11/033,588 →
Memory Cell Having Enhanced High-K Dielectric
Application:
11/008,233 →
Etch Stop Layer for Memory Cell Reliability Improvement
Application:
11/008,240 →