Method for controlling poly 1 thickness and uniformity in a memory array fabrication process
View Patent ↗According to one exemplary embodiment, a method includes planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, where the polysilicon segments have top surfaces that are substantially planar with top surfaces of the field oxide regions, and where the field oxide regions have a first height and the polysilicon segments have a first thickness. The method further includes removing a hard mask over a peripheral region of the substrate. According to this exemplary embodiment, the method further includes etching the polysilicon segments to cause the polysilicon segments to have a second thickness, which causes the top surfaces of the polysilicon segments to be situated below the top surfaces of the field oxide regions. The polysilicon segments can be etched by using a wet etch process. The polysilicon segments are situated in a core region of the substrate.
1. A method comprising:
planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, said polysilicon segments having top surfaces that are substantially planar with top surfaces of said field oxide regions, said field oxide regions having a first height and said polysilicon segments having a first thickness;
etching said polysilicon segments to cause said polysilicon segments to have a second thickness, said step of etching said polysilicon segments causing said top surfaces of said polysilicon segments to be situated below said top surfaces of said field oxide regions, said polysilicon segments being situated in a core region of said substrate;
recessing said field oxide regions to cause said field oxide regions to have a second height, said second height being substantially equal to said second thickness of said polysilicon segments.
2. The method of claim 1 wherein said step of etching said polysilicon segments comprises using a wet etch process.
3. The method of claim 1 wherein said step of etching said polysilicon segments and said step of recessing said field oxide regions are performed in a single process tool.
4. The method of claim 1 further comprising a step of removing a hard mask over a peripheral region of said substrate prior to said step of etching said polysilicon segments, wherein said step of etching said polysilicon segments, said step of removing said hard mask, and said step of etching said polysilicon segments are performed in a single process tool.
5. The method of claim 1 wherein said step of planarizing said layer of polysilicon comprises using a chemical mechanical polishing process.
6. The method of claim 1 wherein said first height of said field oxide regions is equal to a distance between a gate oxide layer situated on said substrate and said top surfaces of said field oxide regions.
7. The method of claim 1 wherein said second thickness of said polysilicon segments is less than 600.0 Angstroms.
8. The method of claim 1 further comprising a step of removing a hard mask over a peripheral region of said substrate prior to said step of etching said polysilicon segments.
9. The method of claim 8 wherein said step of etching said polysilicon segments and said step of removing said hard mask are performed in a single process tool.
10. A method of fabricating a memory array, said method comprising:
planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, said polysilicon segments having top surfaces that are substantially planar with top surfaces of said field oxide regions, said field oxide regions having a first height and said polysilicon segments having a first thickness, said polysilicon segments being situated in a core region of said substrate;
removing a hard mask situated over a peripheral region of said substrate;
etching said polysilicon segments to cause said polysilicon segments to have a second thickness, said step of etching said polysilicon segments causing said top surfaces of said polysilicon segments to be situated below said top surfaces of said field oxide regions;
wherein said step of removing said hard mask is performed prior to said step of etching said polysilicon segments;
recessing said field oxide regions to cause said field oxide regions to have a second height, said second height being substantially equal to said second thickness of said polysilicon segments.
11. The method of claim 10 wherein said step of etching said polysilicon segments comprises using a wet etch process, wherein said wet etch process causes substantially no etching of said field oxide regions.
12. The method of claim 10 wherein said step of removing said hard mask, said step of etching said polysilicon segments, and said step of recessing said field oxide regions are performed in a single process tool.
13. The method of claim 10 wherein said step of etching said polysilicon segments and said step of removing said hard mask are performed in a single process tool.
14. The method of claim 10 wherein said step of etching said polysilicon segments comprises using an ammonia peroxide mixture.
15. The method of claim 10 wherein said first height of said field oxide regions is equal to a distance between a gate oxide layer situated on said substrate and said top surfaces of said field oxide regions.
16. The method of claim 10 wherein said second thickness of said polysilicon segments is less than 600.0 Angstroms.
17. The method of claim 10 wherein said step of planarizing said layer of polysilicon comprises using a chemical mechanical polishing process.
18. The method of claim 17 wherein said first height of said field oxide regions determines an endpoint of said chemical mechanical polishing process.