Memory cell having enhanced high-K dielectric
View Patent ↗A semiconductor memory device may include an intergate dielectric layer of a high-K, high barrier height dielectric material interposed between a charge storage layer and a control gate. With this intergate high-K, high barrier height dielectric in place, the memory device may be efficiently erased using Fowler-Nordheim tunneling.
1. A memory device comprising:
a gate dielectric formed on a substrate;
a charge storage layer formed on the gate dielectric;
a single intergate dielectric layer formed on the charge storage layer, the single intergate dielectric layer including a first material having a dielectric constant (K) value to prevent back gate injection and a second material having a barrier height to reduce current leakage,
wherein the first material and the second material are mixed together and wherein the single intergate dielectric layer has a thickness of between about 90 and 210 Å and a barrier height of between about 1.7 and 3.5 electron volts (eV); and
a control gate formed above the single intergate dielectric layer.
2. The memory device of claim 1 , wherein the single intergate dielectric layer has a K value greater than that of SiO 2 and a barrier height greater than that of HfO 2 .
3. The memory device of claim 1 , wherein the first material comprises at least one of hafnium silicate, hafnium silicon oxynitride, hafnium silicon nitride, hafnium dioxide, zirconium dioxide, or tantalum oxide and wherein the second material comprises at least one of aluminum oxide or silicon dioxide.
4. The memory device of claim 3 , wherein the single intergate dielectric layer includes a mixture of hafnium dioxide and aluminum oxide in a ratio of about 4:1.
5. The memory device of claim 3 , wherein the single intergate dielectric layer includes a mixture of hafnium dioxide and silicon dioxide in a ratio ranging from about 4:1 to about 1:4.
6. The memory device of claim 5 , wherein the single intergate dielectric layer has a thickness of between about 90 and about 210 Å.
7. An integrated circuit comprising:
an array of memory cells formed on a semiconductor substrate, each of the memory cells including:
a gate dielectric formed on the substrate,
a charge storage layer formed on the gate dielectric,
an single intergate dielectric layer formed on the charge storage layer, the single intergate dielectric layer comprising an about 4:1 mixture of a first material having a high dielectric constant (K) value and a second material having a high barrier height,
and
a control gate formed above the single intergate dielectric layer.
8. The integrated circuit of claim 7 , further comprising:
a programming circuit configured to perform an erase operation of one or more of the memory cells in the array by removing charge from the charge storage layer using Fowler-Nordheim tunneling,
wherein the single intergate dielectric layer has a K value greater than that of silicon dioxide.
9. The integrated circuit of claim 8 , wherein the first material comprises at least one of hafnium silicate, hafnium silicon oxynitride, hafnium silicon nitride, hafnium dioxide, zirconium dioxide, or tantalum oxide and wherein the second material comprises at least one of aluminum oxide or silicon dioxide.
10. The integrated circuit of claim 9 , wherein the single intergate dielectric layer comprises a mixture of hafnium dioxide and aluminum oxide having a barrier height between about 1.5 and 3.9.
11. The integrated circuit of claim 9 wherein the single intergate dielectric layer has a thickness of between about 90 and about 210 Å.