Interlayer dielectric for charge loss improvement
View Patent ↗A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes forming a second dielectric layer over the charge storage element and forming a control gate over the second dielectric layer. The method further includes depositing an interlayer dielectric over the control gate at a high temperature.
1. A method of manufacturing a memory device, comprising:
forming a first dielectric layer over a substrate;
forming a charge storage element over the first dielectric layer;
forming a second dielectric layer over the charge storage element;
forming a control gate over the second dielectric layer; and
depositing an interlayer dielectric over the control gate at a temperature greater than about 650° C.
2. The method of claim 1 , wherein the interlayer dielectric comprises boro-phosphosilicate glass.
3. The method of claim 1 , wherein the depositing the interlayer dielectric comprises depositing the interlayer dielectric to a thickness ranging from about 5,500 Å to about 8,500 Å.
4. The method of claim 1 , further comprising:
forming a silicide over the control gate.
5. The method of claim 4 , wherein the forming a silicide comprises:
depositing a metal over the control gate, and
annealing the semiconductor device to form a metal-silicide compound.
6. The method of claim 5 , wherein the metal-silicide compound comprises cobalt silicide.
7. The method of claim 1 , wherein the deposited interlayer dielectric is substantially free of voids without requiring a densification procedure.
8. The method of claim 1 , further comprising:
forming a plurality of memory cells, each of the memory cells being configured to store charges representing two bits of information.
9. A method of manufacturing a non-volatile memory device, comprising:
forming a plurality of memory cells; and
depositing an interlayer dielectric over the plurality of memory cells at a temperature greater than 650° C.
10. The method of claim 9 , wherein the interlayer dielectric comprises boro-phosphosilicate glass.
11. The method of claim 10 , wherein the depositing the interlayer dielectric comprises depositing the interlayer dielectric to a thickness ranging from about 5,500 Å to about 8,500 Å.
12. The method of claim 9 , wherein each of the memory cells includes a first dielectric layer formed over a substrate, a charge storage element formed over the first dielectric layer, a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer, the method further comprising:
forming a silicide over the control gate.
13. The method of claim 12 , wherein the forming a silicide comprises:
depositing a metal over the control gate, and
annealing the semiconductor device to form a metal-silicide.
14. The method of claim 13 , wherein the metal comprises at least one of cobalt, titanium or nickel.
15. The method of claim 9 , further comprising:
depositing a conductive layer over the interlayer dielectric without performing a densification process with respect to the interlayer dielectric; and
depositing a second interlayer dielectric over the conductive layer at a temperature ranging from 300° C. to 400° C.
16. The method of claim 9 , wherein each of the plurality of memory cells stores charges representing two bits of information.
17. A method of manufacturing a non-volatile memory device, comprising:
forming a first dielectric layer over a substrate;
forming a charge storage element over the first dielectric layer, the charge storage element comprising a nitride;
forming a second dielectric layer over the charge storage element;
forming a control gate electrode over the second dielectric layer; and
depositing an interlayer dielectric over the control gate electrode at a temperature greater than 600° C.
18. The method of claim 17 , further comprising:
forming a silicide over a top surface of the control gate electrode, the silicide having a substantially smooth upper surface.
19. The method of claim 17 , wherein the interlayer dielectric comprises at least one of boro-phosphosilicate glass or phosphosilicate glass.
20. The method of claim 17 , wherein the charge storage element associated with each memory cell in the non-volatile memory device is configured to store charges representing two bits of information.