IP Library Granted Patent US 8,022,468
Granted Patent B1
US 8,022,468 · App. 11/091,519 · Granted Sep 20, 2011

Ultraviolet radiation blocking interlayer dielectric

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Quick Facts
Patent No.
US 8,022,468
App. No.
11/091,519
Granted
Sep 20, 2011
Kind
B1
Abstract

A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer. The memory device may further include an interlayer dielectric formed over the control gate and the substrate, where the interlayer dielectric includes a material that is substantially opaque to ultraviolet radiation.

Claims (41)

1. A memory device, comprising:

a substrate;

a first dielectric layer formed over the substrate;

a charge storage element formed over the first dielectric layer;

a second dielectric layer formed over the charge storage element;

a control gate formed over the second dielectric layer;

a single layer formed over the control gate and the substrate and physically contacting an upper surface of the substrate, the single layer comprising a first interlayer dielectric comprising a silicon-rich silicon nitride having a refractive index ranging from 2.2 to 2.5, where the silicon-rich silicon nitride has a thickness ranging from about 250 Å to about 650 Å;

at least one conductive layer formed over the single layer;

at least one second interlayer dielectric formed over the at least one conductive layer, the at least one second interlayer dielectric comprising a material that blocks at least 95 percent of ultraviolet radiation; and

another conductive layer formed over the at least one second interlayer dielectric, where the at least one second interlayer dielectric includes a contact hole that is filled by a metal layer that connects to the at least one conductive layer and the another conductive layer.

2. The memory device of claim 1 , further comprising:

a third interlayer dielectric formed over the first interlayer dielectric.

3. The memory device of claim 2 , where the third interlayer dielectric comprises boro-phosphosilicate glass.

4. A semiconductor device, comprising:

a plurality of memory cells formed on a substrate;

a continuous layer formed over the plurality of memory cells and physically contacting an upper surface of the substrate, the continuous layer comprising a first material having a refractive index of about 2.5, where the first material comprises a silicon-rich silicon nitride and has a thickness ranging from about 250 Å to about 650 Å;

a conductive layer formed over the continuous layer;

an interlayer dielectric formed over the conductive layer, the interlayer dielectric comprising a material that blocks at least 95 percent of ultraviolet radiation; and

another conductive layer formed over the interlayer dielectric, where the interlayer dielectric includes a contact hole that is filled by a metal layer that connects to the conductive layer and the another conductive layer.

5. The semiconductor device of claim 4 , where the continuous layer blocks at least 95 percent of ultraviolet radiation from reaching the plurality of memory cells.

6. The semiconductor memory device of claim 4 , where each of the plurality of memory cells comprises:

a tunnel layer formed over the substrate,

a charge storage element formed over the tunnel layer, the charge storage element comprising a dielectric material,

an inter-gate dielectric formed over the charge storage element, and

a control gate formed over the inter-gate dielectric.

7. The semiconductor device of claim 6 , where each of the plurality of memory cells is to store two bits of information.

8. A non-volatile memory device, comprising:

a substrate;

a first dielectric material formed over the substrate;

a charge storage element formed over the first dielectric material;

a second dielectric material formed over the charge storage element;

a control gate formed over the second dielectric material;

a continuous first interlayer dielectric formed over the control gate and physically contacting an upper surface of the substrate, the continuous first interlayer dielectric comprising a material that has a refractive index of about 2.5, and has a thickness ranging from about 250 Å to about 650 Å, where the first interlayer dielectric comprises a silicon-rich silicon nitride;

a conductive layer formed over the continuous first interlayer dielectric;

a second interlayer dielectric formed over the conductive layer, the second interlayer dielectric comprising a material that blocks at least 95 percent of ultraviolet radiation;

another conductive layer formed over the second interlayer dielectric, where the second interlayer dielectric includes a contact hole that is filled by a metal layer that connects to the conductive layer and the another conductive layer; and

a cap layer formed over the second interlayer dielectric, the cap layer comprising the material that has a refractive index of about 2.5.

9. The non-volatile memory device of claim 8 , where the continuous first interlayer dielectric blocks about 95 percent to about 100 percent of ultraviolet radiation from reaching the control gate.

10. The non-volatile memory device of claim 8 , where the charge storage element for each memory cell in the non-volatile memory device is to store two bits of information.

11. The non-volatile memory device of claim 8 , where the cap layer has a thickness ranging from about 6,000 Å to about 10,000 Å.

12. The non-volatile memory device of claim 8 , where the cap layer blocks at least 95 percent of ultraviolet radiation.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2017
From: ADVANCED MICRO DEVICES, INC.
To: SPANSION LLC
Reel/Frame 042416/0448 →
RELEASE OF SECURITY INTEREST Recorded Dec 17, 2015
From: BARCLAYS BANK PLC, AS COLLATERAL AGENT
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC; SPANSION TECHNOLOGY INC.
Reel/Frame 037315/0700 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
SECURITY AGREEMENT Recorded Aug 23, 2012
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 028840/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2005
From: NGO, MINH VAN; LI, WENMEI; SHIELDS, JEFFREY A.; CHENG, NING; CHEN, CINTI XIAOHUA
To: SPANSION LLC
Reel/Frame 016422/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2005
From: HUI, ANGELA
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 016422/0807 →