Memory cell system with charge trap
View Patent ↗A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.
1. A memory cell system comprising:
a first insulator layer over a semiconductor substrate;
a charge trap layer over the first insulator layer, the charge trap layer including a second insulator layer; and
a third insulator layer over the second insulator layer, the third insulator layer comprising at least a portion of the second insulator layer converted to oxide wherein an interface between the charge trap layer and the third insulator layer is smoother than a thermal oxide interface.
2. The system as claimed in claim 1 wherein the charge trap layer comprises a nitride.
3. The system as claimed in claim 1 wherein the charge trap layer comprises silicon and nitrogen.
4. The system as claimed in claim 1 wherein the charge trap layer has multiple layers comprised of a silicon rich nitride layer over the first insulator layer and a layer of nitride with less silicon content over the silicon rich nitride layer.
5. The system as claimed in claim 1 further comprising:
a memory system with memory cell systems; and
a device or an electronic system with the memory system.
6. The system as claimed in claim 1 wherein:
the first insulator layer is a tunneling oxide layer over the semiconductor substrate;
the second insulator layer is a nitride layer over the first insulator layer; and
the third insulator layer, having substantially uniform thickness, is a blocking oxide layer on the charge trap layer.
7. The system as claimed in claim 6 wherein the tunneling oxide layer is a silicon dioxide layer.
8. The system as claimed in claim 6 wherein the nitride layer over the tunneling oxide layer has silicon and nitrogen.
9. The system as claimed in claim 6 wherein the nitride layer has a gradient concentration of the silicon in the nitride layer.
10. The system as claimed in claim 6 further comprising a conductive gate electrode on the blocking oxide layer.
11. The system as claimed in claim 1 wherein the third insulator layer has been grown from the second insulator layer using a slot plane antenna plasma technique.
12. A memory cell system comprising:
a tunneling layer over a semiconductor substrate;
a charge trap layer over the tunneling layer, the charge trap layer including a nitride layer; and
a blocking layer over the charge trap layer, the blocking layer comprising at least a portion of the nitride layer converted to oxide, wherein an interface between the charge trap layer and the blocking layer is smoother than a thermal oxide interface.
13. The system as claimed in claim 12 wherein the charge trap layer includes a silicon rich nitride layer, the nitride layer being less silicon rich then the silicon rich nitride layer.
14. The system as claimed in claim 12 wherein the charge trap layer has multiple layers comprised of a silicon rich nitride layer over tunneling layer and a layer of nitride with less silicon content over the silicon rich nitride layer.
15. The system as claimed. in claim 12 further comprising:
a memory system with memory cell systems; and
a device or an electronic system with the memory system.
16. The system as claimed in claim 12 wherein:
the tunneling layer is a tunneling oxide layer; and
the blocking layer is a top blocking oxide layer on the charge trap layer, the blocking layer having a uniform interface with the nitride layer.
17. The system as claimed in claim 16 wherein the tunneling oxide layer is a silicon dioxide layer.
18. The system as claimed in claim 16 wherein the nitride layer has a gradient concentration of the silicon in the nitride layer.
19. The system as claimed in claim 12 wherein the blocking layer has been grown from the nitride layer using a slot plane antenna plasma technique.