Gap-filling with uniform properties
View Patent ↗During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 Å to about 500 Å, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.
1. A method of fabricating a semiconductor device, the method comprising:
depositing a first layer of dielectric material into a gap between two spaced apart gate electrode structures;
curing the first deposited layer of dielectric material;
depositing a second layer of dielectric material on the first deposited layer of dielectric material and into the gap;
curing the deposited second layer of dielectric material, wherein:
the first dielectric layer comprises boron and phosphorous-doped tetraethyl orthosilicate (BPTEOS);
the second dielectric layer comprises BPTEOS;
the first dielectric layer contains a greater amount of boron than the second dielectric layer; and
the second dielectric layer contains a greater amount of phosphorous than the first dielectric layer.
2. The method according to claim 1 , wherein each layer of dielectric material is deposited at a thickness of about 10 Å to about 500 Å, and each layer of dielectric material is cured after it is deposited by either heating at a temperature of about 400° C. to about 1000° C. or exposing the layer to ultraviolet (UV) radiation.
3. The method according to claim 1 , wherein each gate electrode structure comprises a dielectric sidewall spacer on side surfaces thereof.
4. The method according to claim 1 , wherein the first and second dielectric layers comprise the same dielectric material.
5. The method according to claim 1 , wherein the first and second dielectric layers comprise different dielectric materials.
6. The method according to claim 3 , wherein each gate electrode structure further comprises:
a gate dielectric stack comprising a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer; and
a gate electrode on the gate dielectric stack.
7. The method according to claim 5 , wherein each dielectric layer comprises the same dielectric material.
8. A semiconductor device prepared by a process comprising:
depositing a first layer of dielectric material into a gap between two spaced apart gate electrode structures;
curing the first deposited layer of dielectric material;
depositing a second layer of dielectric material on the first deposited layer of dielectric material and into the gap;
curing the deposited second layer of dielectric material, wherein:
the first dielectric layer comprises boron and phosphorous-doped tetraethyl orthosilicate (BPTEOS);
the second dielectric layer comprises BPTEOS;
the first dielectric layer contains a greater amount of boron than the second dielectric layer; and
the second dielectric layer contains a greater amount of phosphorous than the first dielectric layer.
9. The semiconductor device of claim 8 , wherein each layer of dielectric material is deposited at a thickness of about 10 Å to about 500 Å, and each layer of dielectric material is cured after it is deposited by either heating at a temperature of about 400° C. to about 1000° C. or exposing the layer to ultraviolet (UV) radiation.
10. The semiconductor device of claim 8 , wherein each gate electrode structure comprises a dielectric sidewall spacer on side surfaces thereof.
11. The semiconductor device of claim 8 , wherein the first and second dielectric layers comprise the same dielectric material.
12. The semiconductor device of claim 8 , wherein the first and second dielectric layers comprise different dielectric materials.
13. The semiconductor device of claim 10 , wherein each gate electrode structure further comprises:
a gate dielectric stack comprising a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer; and
a gate electrode on the gate dielectric stack.
14. The semiconductor device of claim 12 , wherein each dielectric layer comprises the same dielectric material.