Disposable hard mask for forming bit lines
View Patent ↗A method includes forming a group of disposable hard mask structures on a semiconductor device that includes a group of memory cells. The method further includes using the disposable hard mask structures to precisely control a junction profile of the memory cells.
1. A method comprising:
forming a hard mask layer on a semiconductor device;
forming a photoresist layer;
patterning the photoresist layer;
etching the hard mask layer using the patterned photoresist layer to form a plurality of hard mask structures, where each of the plurality of hard mask structures has a substantially rectangular cross-sectional shape, and
where the plurality of hard mask structures is formed at a pitch ranging from about 900 Å to about 2,400 Å; and
performing an ion implantation to form source or drain junctions between successive hard mask structures.
2. The method of claim 1 further comprising:
removing the hard mask structures after performing the ion implantation.
3. The method of claim 1 where the forming the hard mask layer comprises:
forming the hard mask layer to a thickness ranging from about 500 Å to about 5,000 Å.
4. The method of claim 1 where the hard mask layer comprises at least one of a carbon-based material or a material comprising a polymer.
5. The method of claim 1 further comprising:
forming an additional layer between the hard mask layer and the photoresist layer.
6. The method of claim 5 where the additional layer comprises an anti-reflective coating.
7. The method of claim 5 where the additional layer comprises an additional hard mask layer.
8. The method of claim 5 where the forming an additional layer comprises:
forming the additional layer to a thickness ranging from about 100 Å to about 3,000 Å.
9. The method of claim 1 where a width of each source or drain junction ranges from about 200 Å to about 600 Å and a depth ranging from about 200 Å to about 3,000 Å.
10. The method of claim 1 where a first side of at least one of the source or drain junctions is substantially aligned with a side wall of a first one of the plurality of hard mask structures and a second side of the at least one of the source or drain junctions is substantially aligned with a side wall of a second one of the plurality of hard mask structures.
11. A method comprising:
forming a plurality of disposable hard mask structures on a semiconductor device comprising a plurality of memory cells, where the plurality of disposable hard mask structures is formed at a pitch ranging from about 900 Å to about 2,400 Å; and
using the plurality of disposable hard mask structures to precisely control a junction profile of the plurality of memory cells.
12. The method of claim 11 where the disposable hard mask structures comprise a material having a low dielectric constant.
13. The method of claim 11 where each of the plurality of disposable hard mask structures comprises a top section and a bottom section, the top section comprising a first material and the bottom section comprising a second material.
14. The method of claim 13 where the first material comprises an anti-reflective coating and the second material comprises a material with a low dielectric constant.
15. The method of claim 11 further comprising:
removing the plurality of hard mask structures after forming junctions for the plurality of memory cells.
16. The method of claim 11 where the forming a plurality of disposable hard mask structures comprises:
forming each of the plurality of disposable hard mask structures to a width ranging from 450 Å to about 1,200 Å and a height ranging from about 500 Å to about 5,000 Å.
17. The method of claim 11 where the plurality of hard mask structures have a substantially rectangular cross-sectional shape.
18. A method for forming a bit line comprising:
forming a plurality of hard mask structures using a photoresist, each hard mask structure being formed to a width ranging from 450 Å to about 1,200 Å and a height ranging from about 500 Å to about 5,000 Å, and where each of the plurality of hard mask structures has a substantially rectangular cross-sectional shape, and
where the plurality of hard mask structures is formed at a pitch ranging from about 900 Å to about 2,400 Å;
performing a first implant process to form the bit line after forming the plurality of hard mask structures; and
removing the plurality of hard mask structures after performing the first implant process.
19. The method of claim 18 where the forming comprises:
forming a hard mask layer on a semiconductor device,
forming a photoresist layer,
patterning the photoresist layer, and
etching the hard mask layer using the patterned photoresist layer to form the plurality of hard mask structures.