Granted Patent B1

US 8,415,256 · App. 12/982,364 · Granted Apr 9, 2013

Abstract

Claims (29)

1. A method of fabricating a semiconductor device, the method comprising:

depositing a first layer of dielectric material into a layer feature comprising an opening of a layer or a gap between elements;

depositing a second layer of dielectric material on the first deposited layer of dielectric material and into the layer feature; and

separately curing the first and second layers after each layer is deposited;

wherein the first dielectric layer comprises boron and phosphorous-doped tetraethyl orthosilicate (BPTEOS), and the second dielectric layer comprises BPTEOS; and

wherein the first dielectric layer contains a greater amount of boron than the second dielectric layer, and the second dielectric layer contains a greater amount of phosphorous than the first dielectric layer.

2. The method of claim 1 , comprising:

depositing at least one additional layer of dielectric material into the layer feature; and

separately curing each additional layer of dielectric material after deposition.

3. The method of claim 1 , further comprising:

depositing each layer of dielectric material at a thickness of about 10 Å; and separately curing each layer of dielectric material by either heating at a temperature of about 400° C. to about 1000° C., or exposing the layer to ultraviolet (UV) radiation.

4. The method of claim 1 , wherein the layer feature is a shallow trench in a semiconductor substrate, the method comprising filling the trench with the layers of dielectric material, with intermediate post deposition curing, to form a shallow trench isolation (STI) structure.

5. The method of claim 1 , comprising depositing the layers of dielectric material into a gap between two spaced apart gate electrode structures.

6. The method of claim 1 , wherein:

the first layer of dielectric material comprises boron-doped silicon oxide derived from tetraethyl orthosilicate (BTEOS); and the second dielectric layer comprises phosphorous-doped tetraethyl orthosilicate (PTEOS).

7. The method according to claim 1 , wherein the first and second dielectric layers comprise the same dielectric material.

8. The method according to claim 1 , wherein the first and second dielectric layers comprise different dielectric materials.

9. The method of claim 2 , comprising:

depositing three to six layers of dielectric material; and

separately curing each layer of dielectric material after deposition.

10. The method of claim 2 , comprising:

depositing each layer of dielectric material at a thickness of about 10 Å to about 500 Å; and

separately curing each layer of dielectric material after deposition by either heating at a temperature of about 400° C. to about 1000° C., or exposing the layer to ultraviolet (UV) radiation.

11. The method of claim 2 , wherein the layer feature is a shallow trench in a semiconductor substrate, the method comprising filling the trench with the layers of dielectric material, with intermediate post deposition curing, to form a shallow trench isolation (STI) structure.

12. The method according to claim 4 , wherein each dielectric layer comprises the same dielectric material.

13. The method of claim 5 , wherein each gate electrode structure comprises a dielectric sidewall spacer on side surfaces thereof.

14. The method of claim 5 , wherein each gate electrode structure comprises:

a gate dielectric stack comprising a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer; and

a gate electrode on the gate dielectric stack.

Assignments (6)