Semiconductor memory device
View Patent ↗A drain ( 7 ) includes a lightly-doped shallow impurity region ( 7 a ) aligned with a control gate ( 5 ), and a heavily-doped deep impurity region ( 7 b ) aligned with a sidewall film ( 8 ) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region ( 7 a ). The lightly-doped shallow impurity region ( 7 a ) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion ( 70 ) is provided to the heavily-doped impurity region ( 7 b ) to reduce the contact resistance at the drain ( 7 ).
1. A manufacturing method of a semiconductor memory device comprising the steps of:
forming a gate electrode by patterning on a semiconductor substrate via a gate insulating film;
forming one diffusion layer by doping impurities into such a surface layer of the semiconductor substrate that is at one side of the gate electrode;
forming a lightly-doped impurity region by doping impurities into such a surface layer of the semiconductor substrate that is at other side of the gate electrode at a concentration lower than the concentration of the other side of the gate electrode;
forming a pair of sidewall films on side surfaces of the gate electrode; and
forming a heavily-doped impurity region partially overlapping the lightly-doped impurity region by doping a high concentration of impurities into such a surface layer of the semiconductor substrate that is at the other side of the sidewall film as well as the gate electrode to thereby form other diffusion layer composed of the lightly-doped impurity region and the heavily-doped impurity region.
2. The manufacturing method of the semiconductor memory device according to claim 1 ,
wherein the heavily-doped impurity region is formed concurrently with an impurity diffusion layer in a peripheral circuit region.
3. The manufacturing method of the semiconductor memory device according to claim 1 ,
wherein the heavily-doped impurity region is formed by forming a resist mask of a shape exposing only a forming portion of the heavily-doped impurity region and by performing ion-implantation of impurities using the resist mask.
4. The manufacturing method of the semiconductor memory device according to claim 1 ,
wherein the heavily-doped impurity region is formed by forming a resist mask of a shape including a contact hole forming portion of the one diffusion layer and crossing the gate electrode, and by performing ion-implantation of impurities using the resist mask.
5. The manufacturing method of the semiconductor memory device according to claim 1 ,
wherein the heavily-doped impurity region is formed by forming a resist mask of a shape covering only a contact hole forming portion of the one diffusion layer, and by performing ion-implantation of impurities using the resist mask.
6. The manufacturing method of the semiconductor memory device according to claim 1 ,
wherein the sidewall film is formed to cover a surface of the one diffusion layer.
7. A manufacturing method of a semiconductor memory device comprising the steps of:
forming a floating gate having an island structure and storing electric charges by patterning on a semiconductor substrate via a first gate insulating film;
forming a control gate by patterning on the floating gate via a second gate insulating film;
forming one diffusion layer by doping impurities into such a surface layer of the semiconductor substrate that is at one side of the control gate;
forming a lightly-doped impurity region by doping impurities into such a surface layer of the semiconductor substrate that is at other side of the control gate at a concentration lower than the concentration of the one side of the control gate;
forming a pair of sidewall films on side surfaces of the control gate; and
forming a heavily-doped impurity region partially overlapping the lightly-doped impurity region by doping a high concentration of impurities into such a surface layer of the semiconductor substrate that is at the other side of the sidewall film as well as the control gate to thereby form other diffusion layer composed of the lightly-doped impurity region and the heavily-doped impurity region.
8. The manufacturing method of the semiconductor memory device according to claim 7 ,
wherein the heavily-doped impurity region is formed concurrently with an impurity diffusion layer in a peripheral circuit region.
9. The manufacturing method of the semiconductor memory device according to claim 7 ,
wherein the heavily-doped impurity region is formed by forming a resist mask of a shape exposing only a forming portion of the heavily-doped impurity region and by performing ion-implantation of impurities using the resist mask.
10. The manufacturing method of the semiconductor memory device according to claim 7 ,
wherein the heavily-doped impurity region is formed by forming a resist mask of a shape including a contact hole forming portion of the one diffusion layer and crossing the gate electrode, and by performing ion-implantation of impurities using the resist mask.
11. The manufacturing method of the semiconductor memory device according to claim 7 ,
wherein the heavily-doped impurity region is formed by forming a resist mask of a shape covering only a contact hole forming portion of the one diffusion layer, and by performing ion-implantation of impurities using the resist mask.
12. The manufacturing method of the semiconductor memory device according to claim 7 ,
wherein the sidewall film is formed to cover a surface of the one diffusion layer.