Semiconductor memory device
View Patent ↗A drain ( 7 ) includes a lightly-doped shallow impurity region ( 7 a ) aligned with a control gate ( 5 ), and a heavily-doped deep impurity region ( 7 b ) aligned with a sidewall film ( 8 ) and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region ( 7 a ). The lightly-doped shallow impurity region ( 7 a ) leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion ( 70 ) is provided to the heavily-doped impurity region ( 7 b ) to reduce the contact resistance at the drain ( 7 ).
1. A semiconductor memory device comprising:
a semiconductor substrate;
a gate insulating film formed on said semiconductor substrate;
a plurality of gate electrodes formed on said gate insulating film;
a pair of diffusion layers formed at both sides of at least one of the plurality of the gate electrodes and in a surface layer of said semiconductor substrate; and
a pair of sidewall films formed on side surfaces of each of the plurality of the gate electrodes,
wherein said pair of diffusion layers has one diffusion layer and the other diffusion layer;
the one diffusion layer is composed of a single diffusion layer formed to be aligned with at least one of the plurality of the gate electrodes at a depth from the surface of said semiconductor substrate,
the other diffusion layer includes a first doped impurity region formed to be aligned with at least one of the plurality of the gate electrodes and having a first depth from the surface of said semiconductor substrate,
and a second doped impurity region formed to be aligned with said sidewall film and having a second depth from the surface of said semiconductor substrate which is deeper than the first depth,
wherein the second doped impurity region is provided between the sidewall film of at least one of the plurality of the gate electrodes and sidewall film of the other of the plurality of the gate electrodes.
2. The semiconductor memory device according to claim 1 , wherein a contact hole is provided in said second doped impurity region.
3. The semiconductor memory device according to claim 1 , wherein said sidewall film covers the surface of said one diffusion layer.
4. The semiconductor memory device according to claim 1 , wherein the first doped impurity region has a first impurity concentration and the second doped impurity region has a second impurity concentration to be different from the first impurity concentration.
5. The semiconductor memory device according to claim 1 , wherein the gate electrode includes at least one of a control gate and a floating gate.
6. The semiconductor memory device according to claim 1 , wherein the gate insulating film includes an ONO film.
7. The semiconductor memory device according to claim 1 , wherein said gate electrode includes a control gate as a word line and a bit line is provided orthogonally.
8. The semiconductor memory device according to claim 1 , wherein the semiconductor memory device is a flash memory.
9. The semiconductor memory device according to claim 1 , wherein one diffusion layer of said pair of diffusion layers is, in whole, covered by the sidewall film of at least one of the plurality of the gate electrodes and the sidewall film of another gate electrode from the plurality of the gate electrodes.
10. A semiconductor memory device comprising:
a semiconductor substrate;
a gate insulating film formed above said semiconductor substrate;
a plurality of gate electrodes formed by patterning above said gate insulating film;
a pair of diffusion layers formed at both sides of at least one of the plurality of the gate electrodes and in said semiconductor substrate; and
a pair of sidewall films formed on side surfaces of each of the plurality of the gate electrodes,
wherein one diffusion layer of said pair of diffusion layers is formed to be aligned with at least one of the plurality of the gate electrodes,
wherein other diffusion layer of said pair of diffusion layers includes a first doped impurity region formed to be aligned with at least one of the plurality of the gate electrodes and a second doped impurity region formed to be aligned with said sidewall film, the first doped impurity region is adjacent to the second doped impurity region,
wherein the second doped impurity region is provided between the sidewall film of at least one of the plurality of the gate electrodes and the sidewall film of the other of the plurality of the gate electrodes,
wherein the first doped impurity region is provided under the sidewall films,
wherein the one diffusion layer is a drain and the other diffusion layer is a source and a width of the source is wider than that of the drain at a region where a source contact hole is provided, and
wherein the impurity concentration of the first doped impurity region is lower than that of the one diffusion layer.
11. A semiconductor memory device comprising:
a semiconductor substrate;
a gate insulating film formed above said semiconductor substrate;
a plurality of gate electrodes formed by patterning above said gate insulating film;
a pair of diffusion layers formed at both sides of at least one of the plurality of the gate electrodes and in said semiconductor substrate; and
a pair of sidewall films formed on side surfaces of each of the plurality of the gate electrodes,
wherein one diffusion layer of said pair of diffusion layers is formed to be aligned with at least one of the plurality of the gate electrodes,
wherein other diffusion layer of said pair of diffusion layers includes a first doped impurity region formed to be aligned with at least one of the plurality of the gate electrodes and a second doped impurity region formed to be aligned with said sidewall film, the first doped impurity region is adjacent to the second doped impurity region,
wherein the second doped impurity region is provided between the sidewall film of at least one of the plurality of the gate electrodes and the sidewall film of the other of the plurality of the gate electrodes,
wherein the first doped impurity region is provided under the sidewall films, and
wherein a contact hole is provided in the second doped impurity region and in a region having a wide space formed by bending at least two word lines.
12. A semiconductor memory device comprising:
a semiconductor substrate;
a gate insulating film formed on said semiconductor substrate;
a plurality of gate electrodes formed on said gate insulating film;
a pair of diffusion layers formed at both sides of at least one of the plurality of gate electrodes and in a surface layer of said semiconductor substrate; and
a pair of sidewall films formed on side surfaces of each of the plurality of gate electrodes, wherein said pair of diffusion layers has one diffusion layer and the other diffusion layer;
the one diffusion layer is composed of a single diffusion layer formed to be aligned with at least one of the plurality of the gate electrodes at a depth from the surface of said semiconductor substrate,
the other diffusion layer includes a first doped impurity region formed to be aligned with at least one of the plurality of the gate electrodes and having a first depth from the surface of said semiconductor substrate, and a second doped impurity region formed to be aligned with said sidewall film and having a second depth from the said semiconductor substrate which is deeper than the first depth,
wherein one diffusion layer of said pair of diffusion layers is, in whole, covered by the side wall of at least one of the plurality of the gate electrodes and the side wall of the other of the plurality of the gate electrodes,
wherein the impurity concentration of the first doped impurity region is lower than that of the one diffusion layer.
13. A semiconductor memory device comprising:
a semiconductor substrate;
a gate insulating film formed on said semiconductor substrate;
a plurality of gate electrodes formed on said gate insulating film;
a pair of diffusion layers formed at both sides of at least one of the plurality of the gate electrodes and in a surface layer of said semiconductor substrate; and
a pair of sidewall films formed on side surfaces of each of the plurality of the gate electrodes,
wherein said pair of diffusion layers has one diffusion layer and the other diffusion layer;
the one diffusion layer includes a diffusion layer formed to be aligned with at least one of the plurality of the gate electrodes at a depth from the surface of said semiconductor substrate, but has no diffusion layer formed to be self-aligned with said sidewall film,
the other diffusion layer includes a first doped impurity region formed to be aligned with at least one of the plurality of the gate electrodes and having a first depth from the surface of said semiconductor substrate, and a second doped impurity region formed to be self-aligned with said sidewall film and having a second depth from the surface of said semiconductor substrate which is deeper than the first depth,
wherein the second doped impurity region is provided between the sidewall film of at least one of the plurality of the gate electrodes and the sidewall film of the other of the plurality of the gate electrodes.
14. The semiconductor memory device according to claim 13 ,
wherein the impurity concentration of the first doped impurity region is lower than that of the one diffusion layer.