Method and apparatus for protection against process-induced charging
View Patent ↗A semiconductor device ( 400 ) for improved charge dissipation protection includes a substrate ( 426 ), a layer of semiconductive or conductive material ( 406 ), one or more thin film devices ( 408 ) and a charge passage device ( 414 ). The thin film devices ( 408 ) are connected to the semiconductive or conductive layer ( 406 ) and the charge passage device ( 414 ) is coupled to the thin film devices ( 408 ) and to the substrate ( 426 ) and provides a connection from the thin film devices ( 408 ) to the substrate ( 426 ) to dissipate charge from the semiconductive/conductive layer ( 406 ) to the substrate ( 426 ).
1. A method for forming a semiconductor device, comprising:
providing a substrate;
forming a charge passage device coupled to the substrate;
forming one or more thin film devices coupled to the charge passage device, wherein at least one of the one or more thin film devices includes at least one high impedance thin film device; and
forming an at least semiconductive layer connected to the one or more thin film devices, wherein in-process charges generated therein, during and since formation of the at least semiconductive layer is dissipated to the substrate through a connection provided by the one or more thin film devices and the charge passage device.
2. The method of claim 1 further including:
doping the substrate to form a doped well therein, and wherein the the charge passage device is configured to be coupled to the doped well.
3. The method of claim 1 wherein the forming the one or more thin film devices comprises:
depositing a semiconductive layer; and
doping at least portions of the semiconductive layer to form one or more high impedance thin film resistors.
4. The method of claim 1 wherein the forming the one or more thin film devices comprises:
depositing a semiconductive layer; and
doping at least portions of the semiconductive layer to form one or more high impedance thin film diodes.
5. The method of claim 4 further comprises:
doping at least portions of the semiconductive layer to form one or more P+/Insulator/N+ (PIN) diodes.
6. The method of claim 1 further comprises:
forming the one or more thin film devices and the at least semiconductive layer concurrently such that the one or more thin film devices are integrally formed in the at least semiconductive layer.
7. The method of claim 6 wherein the at least semiconductive layer includes a first portion and a second portion, wherein the one or more thin film devices are integrally formed in the second portion of the at least semiconductive layer to transport charge from the first portion through the second portion thereof to the charge passage device.
8. The method of claim 7 further comprises:
depositing a polysilicon layer to form the first portion and the second portion of the at least semiconductive layer; and
doping the second portion of the polysilicon layer to integrally form the one or more thin film devices therein.
9. The method of claim 7 further comprises:
forming a gate of one or more transistors in the first portion of the at least semiconductive layer.
10. The method of claim 1 further comprises:
forming a gate of one or more transistors in the at least semiconductive layer.
11. The method of claim 1 wherein the forming the at least semiconductive layer comprises:
depositing a polysilicon layer.
12. The method of claim 1 wherein the forming the charge passage device comprises:
forming a gate oxide capacitor.
13. The method for forming a semiconductor device of claim 1 further comprises:
forming a spine connected to each of the one or more thin film devices and the charge passage device to provide the connection from the one or more thin film devices to the substrate to dissipate charge from the at least semiconductive layer to the substrate.
14. The method of claim 13 further comprises:
forming one or more high impedance resistors connected between each of the one or more thin film devices to the spine.
15. The method of claim 1 wherein the charge passage device, the one or more thin film devices and the at least semiconductive layer are at least partially formed in a single polysilicon deposition processing step.
16. The method of claim 1 further comprising:
shorting out the charge passage device before completing formation of the semiconductor device.
17. The method of claim 1 further comprising:
forming memory core devices and periphery devices, and wherein
the forming the charge passage device comprises epitaxially growing a gate oxide layer,
the forming the at least semiconductive layer comprises depositing a first polysilicon layer, and
the forming the one or more thin film devices comprises doping portions of the first polysilicon layer.
18. The method of claim 17 further comprising:
depositing a second polysilicon layer;
masking the first and the second polysilicon layers;
selectively doping the at least semiconductive layer to adjust the impedances of high impedance portions of the one or more thin film devices;
etching the periphery devices;
implanting the memory core devices and the periphery devices; and
shorting the charge passage device before completing formation of the semiconductor device.
19. The method for forming a semiconductor device of claim 1 wherein the step of forming the charge passage device comprises the step of forming a buried contact.
20. The method for forming a semiconductor device of claim 1 wherein the step of forming the charge passage device comprises the step of forming a thin gate oxide charge leakage device for connecting the one or more thin film devices to the substrate.
21. The method for forming a semiconductor device of claim 20 wherein the step of providing the substrate comprises the step of providing a substrate including source-drain contacts and wherein the step of forming the charge passage device comprises the step of forming a metal layer for connecting the one or more thin film devices to the source-drain contacts.