Etch stop layer for memory cell reliability improvement
View Patent ↗A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.
1. A memory device comprising:
a substrate;
a first dielectric layer formed on a portion of the substrate;
a floating gate formed on the first dielectric layer;
a second dielectric layer formed on the floating gate;
a control gate formed on the second dielectric layer;
a first spacer and a second spacer formed on the substrate on opposite sides of the first dielectric layer, the floating gate, the second dielectric layer, and the control gate;
a first film directly contacting:
a top surface of the control gate,
the first spacer,
the second spacer, and
the substrate,
the first film comprising a conformal silicon nitride film having a substantially uniform thickness,
the conformal silicon nitride film filling gaps and crevices along the first dielectric layer, the floating gate, the second dielectric layer, the control gate, and interfaces associated with the first spacer and the second spacer,
the conformal silicon nitride film filling the gaps and the crevices to improve memory cell data retention of the memory device,
the conformal silicon nitride film being deposited using a low pressure chemical vapor deposition (LPCVD) process or using an atomic layer deposition (ALD) process; and
a second film formed directly on the first film,
the second film comprising a non-conformal silicon nitride film having a non-uniform thickness,
a portion of the non-conformal silicon nitride film formed over the top surface of the control gate being thicker than another portion of the non-conformal silicon nitride film formed adjacent the first spacer and the second spacer, and
the non-conformal silicon nitride film being deposited over the conformal silicon nitride film using a plasma enhanced chemical vapor deposition (PECVD) process.
2. The memory device of claim 1 , further comprising a third film formed on the second film, where the third film comprises a conformal silicon nitride film having a substantially uniform thickness.
3. The memory device of claim 1 , where the conformal silicon nitride film has a thickness of less than 1,000 angstroms.
4. The memory device of claim 1 , where the second film has a thickness ranging from about 100 angstroms to about 700 angstroms.
5. The memory device of claim 1 , where a combined thickness of the first film and the second film ranges from about 100 angstroms to about 1,000 angstroms.
6. A memory device comprising:
a substrate;
a first dielectric layer formed on a portion of the substrate;
a floating gate formed on the first dielectric layer;
a second dielectric layer formed on the floating gate;
a control gate formed on the second dielectric layer;
a conformal first silicon nitride film having a substantially uniform thickness,
the conformal first silicon nitride film directly contacting a portion of the substrate,
the conformal first silicon nitride film filling gaps and crevices along the first dielectric layer, the floating gate, the second dielectric layer, the control gate, and interfaces associated with a first spacer and a second spacer, the first spacer and the second spacer being formed on the substrate and on opposite sides of the control gate,
the conformal first silicon nitride film filling the gaps and the crevices to improve memory cell data retention of the memory device,
the conformal first silicon nitride film being deposited using a low pressure chemical vapor deposition (LPCVD) process or using an atomic layer deposition (ALD) process; and
a non-conformal second silicon nitride film formed directly on the conformal first silicon nitride film,
the non-conformal second silicon nitride film having a non-uniform thickness,
a portion of the non-conformal second silicon nitride film formed over a top surface of the control gate being thicker than another portion of the non-conformal second silicon nitride film formed adjacent the first spacer and the second spacer,
the non-conformal second silicon nitride film extending over a source region and a drain region of the substrate, and
the non-conformal second silicon nitride film being deposited over the conformal first silicon nitride film using a plasma enhanced chemical vapor deposition (PECVD) process.
7. The memory device of claim 6 , where
the conformal first silicon nitride film and the non-conformal second silicon nitride film are formed over a surface of the control gate, the first spacer, the second spacer, and the substrate.
8. The memory device of claim 6 , where a thickness of the conformal first silicon nitride film ranges from about 100 angstroms to about 700 angstroms.
9. The memory device of claim 6 , where the conformal first silicon nitride film and the non-conformal second silicon nitride film have a combined thickness of less than 1,000 angstroms.
10. The memory device of claim 6 , further comprising a conformal third silicon nitride film, having a substantially uniform thickness, formed on the non-conformal second silicon nitride film.
11. A memory device comprising:
a substrate;
a first dielectric layer formed on a portion of the substrate;
a floating gate formed on the first dielectric layer;
a second dielectric layer formed on the floating gate;
a control gate formed on the second dielectric layer,
the control gate including a polysilicon material or a germanium material;
a first spacer and a second spacer formed on the substrate and on opposite sides of the control gate;
a first silicon nitride film contacting:
an upper surface of the polysilicon material or the germanium material included in the control gate,
the first spacer,
the second spacer, and
the substrate,
the first silicon nitride film having a substantially uniform thickness ranging from about 100 angstroms to about 700 angstroms,
the first silicon nitride film filling gaps and crevices along the first dielectric layer, the floating gate, the second dielectric layer, the control gate, and interfaces associated with the first spacer and the second spacer,
the first silicon nitride film filling the gaps and the crevices to improve memory cell data retention of the memory device,
the first silicon nitride film being deposited using a low pressure chemical vapor deposition (LPCVD) process or using an atomic layer deposition (ALD) process; and
a second silicon nitride film formed directly on the first silicon nitride film, the second silicon nitride film having a non-uniform thickness,
a portion of the second silicon nitride film formed over the control gate being thicker than other portions of the second silicon nitride film formed adjacent portions of the first silicon nitride film that contact the first spacer and the second spacer,
the second silicon nitride film being deposited over the first silicon nitride film using a plasma enhanced chemical vapor deposition (PECVD) process, and
the first silicon nitride film and the second silicon nitride film having a combined thickness of less than 1,000 angstroms.
12. The memory device of claim 11 , where the first dielectric layer has a thickness ranging from about 70 angstroms to about 110 angstroms,
where the floating gate has a thickness ranging from about 400 angstroms to about 1,200 angstroms,
where the second dielectric layer has a thickness ranging from about 100 angstroms to about 200 angstroms, and
where the control gate has a thickness ranging from about 900 angstroms to about 3,000 angstroms.
13. The memory device of claim 11 , where the first spacer and the second spacer include a dielectric material.
14. The memory device of claim 11 , further comprising a third silicon nitride film, having a substantially uniform thickness, formed on the second silicon nitride film.