IP Library Granted Patent US 7,972,951
Granted Patent B2
US 7,972,951 · App. 12/688,477 · Granted Jul 5, 2011

Memory device etch methods

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Quick Facts
Patent No.
US 7,972,951
App. No.
12/688,477
Granted
Jul 5, 2011
Kind
B2
Abstract

A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane (CF 4 ) and trifluoromethane (CHF 3 ) to etch at least the control gate layer.

Claims (27)

1. A method of manufacturing a memory device, the method comprising:

forming a plurality of layers over a substrate; and

providing an etch chemistry comprising tetrafluoromethane (CF 4 ), trifluoromethane (CHF 3 ), and oxygen (O 2 ) to etch the plurality of layers, where a flow rate of CF 4 to CH 3 ranges from about 70:30 to about 99.99:0.1.

2. The method of claim 1 , where the tetrafluoromethane (CF 4 ) is provided at a flow rate ranging from about 70 standard cubic centimeters per minute (sccm) to about 100 sccm.

3. The method of claim 2 , where the tetrafluoromethane (CF 4 ) is provided at the flow rate ranging from about 70 sccm to about 100 sccm for a period ranging from about 30 seconds to about 50 seconds.

4. The method of claim 1 , where the providing an etch chemistry comprises:

providing the oxygen (O 2 ) at a flow rate ranging from about 0.1 sccm to about 50 sccm.

5. The method of claim 4 , where the oxygen (O 2 ) is provided at the flow rate ranging from about 0.1 sccm to about 50 sccm for a period ranging from about 20 seconds to about 50 seconds.

6. The method of claim 1 , where the memory device has a critical dimension ranging from about 25 nanometers to about 65 nanometers.

7. The method of claim 1 , further comprising:

forming a hard mask over the plurality of layers.

8. The method of claim 7 , where the hard mask layer comprises at least one of an oxide, nitride, or oxynitride.

9. A method of manufacturing a memory device, the method comprising:

forming a plurality of layers over a substrate; and

performing an etch process to etch the plurality of layers, the etch process comprising an etch chemistry including tetrafluoromethane (CF 4 ), trifluoromethane (CHF 3 ), and at least one of octafluorocyclobutane (C 4 F 8 ), hexafluorobutadiene (C 4 F 6 ), or octafluorocyclopentene (C 5 F 8 ), where the at least one of the C 4 F 8 , the C 4 F 6 , or the C 5 F 8 is provided at a flow rate ranging from about 0.1 sccm to about 20 sccm.

10. The method of claim 9 , where the etch chemistry includes providing the tetrafluoromethane (CF 4 ) and the trifluoromethane (CHF 3 ) at a flow rate ratio ranging from about 99.99:0.1 to about 50:50.

11. The method of claim 10 , where the tetrafluoromethane (CF 4 ) is provided at a flow rate ranging from about 50 sccm to about 100 sccm.

12. The method of claim 11 , where the tetrafluoromethane (CF 4 ) is provided at the flow rate ranging from about 50 sccm to about 100 sccm for a period ranging from about 25 seconds to about 60 seconds.

13. The method of claim 9 , where the octafluorocyclobutane (C 4 F 8 ), the hexafluorobutadiene (C 4 F 6 ), or the octafluorocyclopentene (C 5 F 8 ) is provided at the flow rate ranging from about 0.1 sccm to about 20 sccm for a period ranging from about 25 seconds to about 60 seconds.

14. The method of claim 9 , further comprising:

forming a hard mask over the plurality of layers.

15. The method of claim 14 , where the hard mask layer comprises at least one of an oxide, nitride, or oxynitride.

16. The method of claim 9 , where the memory device has a critical dimension ranging from about 80 nanometers to about 150 nanometers.

17. A method of forming a memory device, the method comprising:

forming a plurality of layers over a substrate; and

performing an etch process to etch the plurality of layers, the etch process comprising an etch chemistry including tetrafluoromethane (CF 4 ) and trifluoromethane (CHF 3 ) at a flow rate ratio ranging from about 70:30 to about 99.99:0.1, and

at least one of octafluorocyclobutane (C 4 F 8 ), hexafluorobutadiene (C 4 F 6 ), or octafluorocyclopentene (C 5 F 8 ), where at least one of the C 4 F 8 , the C 4 F 6 , or the C 5 F 8 is provided at a flow rate ranging from about 0.1 sccm to about 20 sccm.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2017
From: ADVANCED MICRO DEVICES, INC.
To: SPANSION LLC
Reel/Frame 042416/0448 →