Semiconductor device and manufacturing method thereof
View Patent ↗To provide a semiconductor device that enables to suppress a defect density of a gate insulating film of an MISFET, gain a sufficient electric characteristic thereof, and make an Equivalent Oxide Thickness (EOT) of the gate insulating film 1.0 nm or less. The MISFETs are formed to have the gate insulating film formed on a main surface of a silicon substrate, and a gate electrode formed on the gate insulating film, wherein the gate insulating film includes a metal silicate layer formed by a metal oxide layer and a silicon oxide layer and the metal silicate layer is formed so as to have concentration gradients of metal and silicon from a silicon substrate side toward a gate electrode side.
1. A semiconductor device provided with a MISFET having:
a silicon substrate;
a gate insulating film formed over a main surface of said silicon substrate; and
a gate electrode formed over said gate insulating film,
wherein said gate insulating film includes a first insulating film formed over said silicon substrate and a metal silicate layer formed over said first insulating film,
wherein said metal silicate layer is composed of a plurality of silicon oxide layers alternatingly laminated with a plurality of metal oxide layers, each of the plurality of silicon oxide layers being laminated so as to be adjacent to at least one corresponding metal oxide layer,
wherein one of said metal oxide layers formed closest to said gate electrode is thicker than another one of said metal oxide layers formed closest to said silicon substrate,
wherein a concentration of silicon in said metal silicate layer is distributed to become higher on a silicon-substrate side than on a gate-electrode side,
wherein a concentration of metal in said metal silicate layer is distributed to become lower on the silicon-substrate side than on the gate-electrode side, and
wherein an Equivalent Oxide Thickness (EOT) of said gate insulating film is 1.0 nm or less.
2. A semiconductor device according to the claim 1 , wherein said metal oxide layers are formed by an ALD (Atomic Layer Deposition) method.
3. A semiconductor device according to the claim 1 , wherein said first insulating film is formed of a silicon oxide film.
4. A semiconductor device according to the claim 1 , wherein said metal oxide layers include Hf.
5. A semiconductor device according to the claim 1 , wherein said metal oxide layers include one of Zr, Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Cd, Tb, Dy, Ho, Er, Tm, Yb or Lu.
6. A semiconductor device according to the claim 1 , wherein thicknesses of said metal oxide layers decrease from the gate-electrode side to the silicon-substrate side.
7. A semiconductor device according to the claim 1 , wherein one of said silicon oxide layers formed closest to said gate electrode is thinner than another one of said silicon oxide layers formed closest to said silicon substrate.
8. A semiconductor device according to the claim 7 , wherein thicknesses of said silicon oxide layers increase from the gate-electrode side to the silicon-substrate side.
9. A semiconductor device provided with a MISFET having:
a semiconductor substrate;
a gate insulating film formed over said semiconductor substrate; and
a gate electrode formed over said gate insulating film;
wherein said gate insulating film includes a first insulating film formed over said semiconductor substrate and a metal silicate layer formed over said first insulating film,
wherein said metal silicate layer is composed of a plurality of silicon oxide layers alternatingly laminated with a plurality of metal oxide layers, each of the plurality of silicon oxide layers being laminated so as to be adjacent to at least one corresponding metal oxide layer,
wherein one of said metal oxide layers formed closest to said gate electrode is thicker than another one of said metal oxide layers formed closest to said silicon substrate,
wherein a concentration of silicon in said metal silicate layer is distributed to become higher on a silicon-substrate side than on a gate-electrode side, and
wherein a concentration of metal in said metal silicate layer is distributed to become lower on the silicon-substrate side than on the gate-electrode side.
10. A semiconductor device according to the claim 9 , wherein said metal oxide layers are formed by an ALD (Atomic Layer Deposition) method.
11. A semiconductor device according to the claim 9 , wherein said first insulating film is formed of a silicon oxide film.
12. A semiconductor device according to the claim 9 , wherein said metal oxide layers include Hf.
13. A semiconductor device according to the claim 9 , wherein said metal oxide layers include one of Zr, Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Cd, Tb, Dy, Ho, Er, Tm, Yb or Lu.
14. A semiconductor device according to the claim 9 , wherein thicknesses of said metal oxide layers decrease from the gate-electrode side to the silicon-substrate side.
15. A semiconductor device according to the claim 9 , wherein one of said silicon oxide layers formed closest to said gate electrode is thinner than another one of said silicon oxide layers formed closest to said silicon substrate.
16. A semiconductor device according to the claim 15 , wherein thicknesses of said silicon oxide layers increase from the gate-electrode side to the silicon-substrate side.