Organic triodes with novel grid structures and method of production
An organic semiconductor device is provided. The device has a first electrode and a second electrode, with an organic semiconductor layer disposed between the first and second electrodes. An electrically conductive grid is disposed within the organic semiconductor layer, which has openings in which the organic semiconductor layer is present. At least one insulating layer may be disposed adjacent to the electrically conductive grid, preferably such that the electrically conductive grid is completely separated from the organic semiconductor layer by the insulating layer. Methods of fabricating the device, and the electrically conductive grid in particular, are also provided.
1. A method of fabricating a device, comprising the steps of:
(a) depositing a first organic semiconductor layer onto a first electrode;
(b) depositing an electrically conductive layer onto the first organic semiconductor layer;
(c) forming openings in the electrically conductive layer with a patterned die;
(d) removing the patterned die;
(e) depositing a second organic semiconductor layer over the patterned electrically conductive layer and the first organic semiconductor layer;
(f) depositing a second electrode onto the second organic semiconductor layer.
2. The method of claim 1 , further comprising the step of depositing at least one insulating layer.
3. The method of claim 2 , wherein the electrically conductive material is completely separated from the first and second organic layers by insulating layers.
4. The method of claim 3 , further comprising the steps of:
depositing a first insulating layer after step (a) and before step (b);
depositing a second insulating layer after step (b) and before step (c);
wherein openings are also formed in the first and second insulating layers during step (c).
5. The method of claim 4 , further comprising the step of:
oxidizing any exposed area of the electrically conductive layer after step (c) and before step (e) to form an additional insulating layer.
6. The method of claim 4 , further comprising the step of:
depositing a side insulating layer after step (d) and before step (e), such that no portion of the electrically conductive layer remains exposed after deposition of the side insulating layer.
7. The method of claim 3 , further comprising the steps of:
depositing a first insulating layer after step (a) and before step (b);
depositing a side insulating layer after step (d) and before step (e), such that no portion of the electrically conductive layer remains exposed after deposition of the side insulating layer.
8. The method of claim 1 , wherein portions of the electrically conductive layer are removed from the device during step (c) to form the openings, by cold welding the portions of the electrically conductive layer to the die.
9. The method of claim 8 , wherein the die has raised portions coated with a non-oxidizing metal.
10. The method of claim 1 , wherein portions of the electrically conductive layer are separated from the electrically conductive layer and pressed into the first organic semiconductor layer during step (c) to form the openings, and wherein the portions of the electrically conductive layer remain in the first electrically conductive layer after step (d).
11. The method of claim 1 , wherein the die has raised portions having a diameter of about 50-200 nm.
12. The method of claim 1 , wherein the die has raised portions having a center to center distance of about 100-400 nm.
13. The method of claim 1 , wherein the first and second organic semiconducting layers are hole conducting materials, and the electrically conductive layer comprises a metal having a work function greater than about 5 eV.
14. The method of claim 1 , wherein the first and second organic semiconducting layers are electron conducting materials, and the electrically conductive layer comprises a metal having a work function less than about 4 eV.
15. The method of claim 2 , wherein the electrically conductive layer comprises a material selected from the group consisting of gold and aluminum, and the insulating layer comprises SiN x .
16. The method of claim 2 , wherein the insulating layer comprises a material selected from the group consisting of SiN x and SiO 2 .
17. The method of claim 2 , wherein the electrically conductive layer has a thickness of about 10-50 nm.
18. The method of claim 2 , wherein the insulating layer has a thickness of about 5-50 nm.
19. The method of claim 1 , wherein the first and second organic semiconductor layers each have a thickness of about 20-200 nm.