Methods for resistive memory element sensing using averaging
View Patent ↗A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element to maintain a constant voltage across the resistive element. The charge reservoir is connected to the voltage supply to provide a current through the resistive element. The current source is connected to the charge reservoir to repeatedly supply a pulse of current to recharge the reservoir upon depletion of electronic charge from the reservoir, and the pulse counter provides a count of the number of pulses supplied by the current source over a predetermined time. The count represents a logic state of the memory cell element.
1. A method of measuring the value of a resistance comprising:
producing a plurality of electrical pulses at a rate related to the resistance;
counting the electrical pulses over a predetermined time period to produce a pulse count; and
evaluating the pulse count to determine the resistance.
2. The method of claim 1 , wherein each electrical pulse comprises a pulse of substantially uniform width.
3. The method of claim 1 , wherein the evaluating comprises comparing the pulse count to a reference pulse count to determine the value of the resistance.
4. The method of claim 3 , wherein the evaluating further comprises determining the resistance as one value if the pulse count is above the reference pulse count and as another value if the pulse count is below the reference pulse count.
5. A method of measuring an impedance comprising:
applying a substantially uniform voltage across the impedance;
flowing a substantially uniform current into the impedance from a charge reservoir;
flowing a plurality of current pulses into the charge reservoir;
controlling the flow of the plurality of current pulses in response to a quantity of charge in the charge reservoir;
counting the plurality of current pulses over a definite time to produce a pulse count; and
relating an impedance value to the pulse count.
6. The method of claim 5 , wherein the impedance comprises an electrical resistance.
7. The method of claim 5 , wherein the impedance comprises a capacitance.
8. The method of claim 5 , wherein the impedance comprises an inductance.
9. A method for making a memory integrated circuit comprising steps of:
assembling a first circuit for conducting current from a capacitor through a resistor, the first circuit including a controlled current source for delivering current to the capacitor;
providing a comparator for comparing a voltage on the capacitor to a reference voltage and supplying a pulse to turn on the current source when the voltage on the capacitor falls below the reference voltage;
operatively connecting a pulse counter to the comparator output for counting pulses generated by the comparator; and
providing a second circuit for determining the value of the resistance based on a count value stored in the pulse counter.
10. The method of claim 9 , further comprising providing a clock input to the comparator, and arranging the comparator such that the output of the comparator changes state only when a clock signal applied to the clock input changes state.
11. The method of claim 9 , further comprising arranging the second circuit to compare the value stored in the pulse counter to a reference value and determine whether the stored value is greater or less than the reference value.
12. The method of claim 11 , further comprising steps of:
assembling the first circuit to include a transistor having a source operatively connected to the capacitor, a gate, and a drain; and
operatively connecting a differential amplifier having a non-inverting input connected to a first reference voltage, an output operatively connected to the gate, and an inverting input operatively connected to the drain and to the resistor.
13. The method of claim 12 , further comprising including in the second circuit a digital comparator adapted to receive the value stored in the pulse counter, receive the reference value, and compare the stored value to the reference value to produce an output.