Noise canceller circuit
View Patent ↗A noise canceller circuit capable of suppressing power supply noise, produced by transition of a data signal, even in case a data signal is increased in speed. The noise canceller circuit includes an output buffer 20 for outputting a first binary signal that may undergo transition at a timing synchronized with clock signals, and a second output buffer 21 for outputting a second binary signal which has undergone transition in case the first binary signal does not undergo transition at the above timing and for outputting the second binary signal without transition in case the first binary signal has undergone transition at the above timing. The respective output circuits of the output buffers 20, 21 are the same and are constructed so that the respective power supply sources VDD and the ground GND are common to the buffer circuits. A capacitor 24 for absorbing the noise is provided across the power supply and the ground.
1. A noise canceller circuit comprising:
a first circuit for outputting a first binary signal that may undergo transition at a timing synchronized with a clock signal; and
a second circuit for causing a second binary signal to undergo transition in case said first binary signal does not undergo transition at said timing, and for outputting a second binary signal which has undergone transition, said second circuit outputting said second binary signal without transition in case said first binary signal does undergo transition at said timing.
2. The noise canceller circuit as defined in claim 1 wherein output circuits of said first and second circuits are of a same configuration and have a power supply and a ground in common.
3. The noise canceller circuit as defined in claim 1 further comprising:
a noise-absorbing capacitor for a power supply of said first circuit and said second circuit.
4. The noise canceller circuit as defined in claim 1 , wherein
a same load is connected to each of the output circuits of said first and second circuits.
5. The noise canceller circuit as defined in claim 1 wherein
the output circuit of said first circuit outputs a balanced output signal.
6. A data transmitting/receiving apparatus comprising a plurality of the noise canceller circuits as defined in claim 1 .
7. A noise canceller circuit comprising:
a first circuit for outputting a first binary signal that may undergo transition at a timing synchronized with a clock signal;
a second circuit for causing a second binary signal to undergo transition in case said first binary signal does not undergo transition at said timing, and for outputting a second binary signal which has undergone transition, said second circuit outputting said second binary signal without transition in case said first binary signal does undergo transition at said timing; and
a cancel data generating circuit for generating an input signal of said second circuit from an input signal of said first circuit and from said clock signals.
8. The noise canceller circuit as defined in claim 7 , wherein said cancel data generating circuit comprises:
a first flipflop circuit for latching an input signal of said first circuit with an edge of said clock signal;
a second flipflop circuit for latching an output signal of said cancel data generating circuit with said edge;
a first Ex-OR circuit supplied with an input signal of said first circuit and with an output signal of said first flipflop circuit; and
a second Ex-OR circuit supplied with a logical inverted signal of an output of said first Ex-OR circuit and with an output signal of said second flipflop circuit, for delivering an output signal of the cancel data generating circuit.
9. The noise canceller circuit as defined in claim 7 further comprising:
a noise-absorbing capacitor for a power supply of said first circuit and said second circuit.
10. The noise canceller circuit as defined in claim 7 wherein output circuits of said first and second circuits are of a same configuration and have a power supply and a ground in common.
11. The noise canceller circuit as defined in claim 7 , wherein
a same load is connected to each of the output circuits of said first and second circuits.
12. The noise canceller circuit as defined in claim 7 wherein
the output circuit of said first circuit outputs a balanced output signal.
13. A data transmitting/receiving apparatus comprising a plurality of the noise canceller circuits as defined in claim 7 .
14. A data transmitting/receiving apparatus comprising a plurality of the noise canceller circuits as defined in claim 8 .
15. A data transmitting/receiving apparatus comprising a plurality of the noise canceller circuits as defined in claim 9 .
16. A data transmitting/receiving apparatus comprising a plurality of the noise canceller circuits as defined in claim 12 .